Op 18-09-2019 om 02:33 schreef Manasi Navare:
> After the state is committed, we readout the HW registers and compare
> the HW state with the SW state that we just committed.
> For Transcdoer port sync, we add master_transcoder and the
> salves bitmask to the crtc_state, hence we need to read those during
> the HW state readout to avoid pipe state mismatch.
>
> v2:
> * Add Transcoder_D and MISSING_CASE (Maarten)
>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxx>
> Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 49 ++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index b0f76e47f5a6..bea3f631ad36 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -10439,6 +10439,52 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
> }
> }
>
> +static void icelake_get_trans_port_sync_config(struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config)
> +{
> + struct drm_device *dev = crtc->base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + u32 trans_port_sync, transcoders, master_select;
> + enum transcoder cpu_transcoder;
> +
> + trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(pipe_config->cpu_transcoder));
> + if (trans_port_sync & PORT_SYNC_MODE_ENABLE) {
> + master_select = trans_port_sync &
> + PORT_SYNC_MODE_MASTER_SELECT_MASK;
> + switch (master_select) {
> + case 1:
> + pipe_config->master_transcoder = TRANSCODER_A;
> + break;
> + case 2:
> + pipe_config->master_transcoder = TRANSCODER_B;
> + break;
> + case 3:
> + pipe_config->master_transcoder = TRANSCODER_C;
> + break;
> + case 4:
> + pipe_config->master_transcoder = TRANSCODER_D;
> + break;
> + default:
> + MISSING_CASE(master_select);
> + }
> +
> + pipe_config->sync_mode_slaves_mask = 0;
> + } else {
> + pipe_config->master_transcoder = INVALID_TRANSCODER;
> +
> + transcoders = BIT(TRANSCODER_EDP) |
> + BIT(TRANSCODER_A) |
> + BIT(TRANSCODER_B) |
> + BIT(TRANSCODER_C);
^Missed one spot for transcoder D.. also EDP is still here?
> + for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
> + trans_port_sync = I915_READ(TRANS_DDI_FUNC_CTL2(cpu_transcoder));
> +
> + if (trans_port_sync & PORT_SYNC_MODE_ENABLE)
> + pipe_config->sync_mode_slaves_mask |= BIT(cpu_transcoder);
> + }
> + }
> +}
> +
> static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config)
> {
> @@ -10535,6 +10581,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->pixel_multiplier = 1;
> }
>
> + if (INTEL_GEN(dev_priv) >= 11)
> + icelake_get_trans_port_sync_config(crtc, pipe_config);
> +
> out:
> for_each_power_domain(power_domain, power_domain_mask)
> intel_display_power_put(dev_priv,
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