== Series Details == Series: TGL TC enabling URL : https://patchwork.freedesktop.org/series/66695/ State : warning == Summary == $ dim checkpatch origin/drm-tip aa9a2d4bd5f2 drm/i915/tgl: Add missing ddi clock select during DP init sequence 6a06996e8b87 drm/i915/tgl: TC helper function to return pin mapping 9c066f860365 drm/i915/tgl: Finish modular FIA support on registers -:242: WARNING:LONG_LINE: line over 100 characters #242: FILE: drivers/gpu/drm/i915/i915_reg.h:2168: +#define _TC_MOD_PORT_ID(has_modular_fia, tc_port) ((has_modular_fia) ? (tc_port) % 2 : (tc_port)) -:242: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #242: FILE: drivers/gpu/drm/i915/i915_reg.h:2168: +#define _TC_MOD_PORT_ID(has_modular_fia, tc_port) ((has_modular_fia) ? (tc_port) % 2 : (tc_port)) -:252: WARNING:LONG_LINE: line over 100 characters #252: FILE: drivers/gpu/drm/i915/i915_reg.h:2171: +#define DFLEXDPMLE1_DPMLETC_MASK(mod, tc_port) (0xf << (4 * (_TC_MOD_PORT_ID(mod, tc_port)))) -:256: WARNING:LONG_LINE: line over 100 characters #256: FILE: drivers/gpu/drm/i915/i915_reg.h:2175: +#define DFLEXDPMLE1_DPMLETC_ML3_2(mod, tc_port) (12 << (4 * (_TC_MOD_PORT_ID(mod, tc_port)))) -:257: WARNING:LONG_LINE: line over 100 characters #257: FILE: drivers/gpu/drm/i915/i915_reg.h:2176: +#define DFLEXDPMLE1_DPMLETC_ML3_0(mod, tc_port) (15 << (4 * (_TC_MOD_PORT_ID(mod, tc_port)))) -:274: WARNING:LONG_LINE: line over 100 characters #274: FILE: drivers/gpu/drm/i915/i915_reg.h:11675: +#define TC_LIVE_STATE_TBT(mod, tc_port) (1 << ((_TC_MOD_PORT_ID(mod, tc_port)) * 8 + 6)) -:275: WARNING:LONG_LINE: line over 100 characters #275: FILE: drivers/gpu/drm/i915/i915_reg.h:11676: +#define TC_LIVE_STATE_TC(mod, tc_port) (1 << ((_TC_MOD_PORT_ID(mod, tc_port)) * 8 + 5)) -:277: WARNING:LONG_LINE: line over 100 characters #277: FILE: drivers/gpu/drm/i915/i915_reg.h:11678: +#define DP_LANE_ASSIGNMENT_MASK(mod, tc_port) (0xf << ((_TC_MOD_PORT_ID(mod, tc_port)) * 8)) -:278: WARNING:LONG_LINE: line over 100 characters #278: FILE: drivers/gpu/drm/i915/i915_reg.h:11679: +#define DP_LANE_ASSIGNMENT(mod, tc_port, x) ((x) << ((_TC_MOD_PORT_ID(mod, tc_port)) * 8)) total: 0 errors, 8 warnings, 1 checks, 243 lines checked 675571336c4f drm/i915/tgl: Fix driver crash when update_active_dpll is called 77a194507dda drm/i915/tgl: Add dkl phy registers fb5057c3fd44 drm/i915/tgl: Add initial dkl pll support 5d7cf4a2d9b6 drm/i915/tgl: Add support for dkl pll write 777ae3564243 drm/i915/tgl: Add dkl phy programming sequences 9a8c52b002c1 drm/i915/icl: Unify disable and enable phy clock gating functions a1c3093ee5cd drm/i915/tgl: Fix dkl phy register space addressing e00f55852bed drm/i915/tgl: Check the UC health of tc controllers after power on c375eb564833 drm/i915: Add dkl phy pll calculations e15b18d1f053 drm/i915/tgl: Use dkl pll hardcoded values 2a0737c7916f drm/i915/tgl: initialize TC and TBT ports _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
