Quoting Daniele Ceraolo Spurio (2019-07-24 03:21:53)
> +static int uc_fw_xfer(struct intel_uc_fw *uc_fw, struct intel_gt *gt,
> + u32 wopcm_offset, u32 dma_flags)
> +{
> + struct intel_uncore *uncore = gt->uncore;
> + u64 offset;
> + int ret;
> +
> + intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> +
> + /* Set the source address for the uCode */
> + offset = uc_fw_ggtt_offset(uc_fw, gt->ggtt) + uc_fw->header_offset;
> + GEM_BUG_ON(upper_32_bits(offset) & 0xFFFF0000);
> + intel_uncore_write_fw(uncore, DMA_ADDR_0_LOW, lower_32_bits(offset));
> + intel_uncore_write_fw(uncore, DMA_ADDR_0_HIGH, upper_32_bits(offset));
> +
> + /* Set the DMA destination */
> + intel_uncore_write_fw(uncore, DMA_ADDR_1_LOW, wopcm_offset);
> + intel_uncore_write_fw(uncore, DMA_ADDR_1_HIGH, DMA_ADDRESS_SPACE_WOPCM);
> +
> + /*
> + * Set the transfer size. The header plus uCode will be copied to WOPCM
> + * via DMA, excluding any other components
> + */
> + intel_uncore_write_fw(uncore, DMA_COPY_SIZE,
> + uc_fw->header_size + uc_fw->ucode_size);
> +
> + /* Start the DMA */
> + intel_uncore_write_fw(uncore, DMA_CTRL,
> + _MASKED_BIT_ENABLE(dma_flags | START_DMA));
> +
> + /* Wait for DMA to finish */
> + ret = intel_wait_for_register_fw(uncore, DMA_CTRL, START_DMA, 0, 100);
> + if (ret)
> + DRM_ERROR("DMA for %s fw failed, err=%d\n",
> + intel_uc_fw_type_repr(uc_fw->type), ret);
Note the errno will never be that interesting here, it's a wait. I would
suggest including DMA_CTL as that looks like it contains status bits as
well as control.
And let's note use DRM_ERROR() if we can help it, and use dev_err() when
applicable. (Might be time for a new crusade.)
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
-Chris
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