On Sat, Jun 22, 2019 at 12:24:10AM +0000, Souza, Jose wrote:
> On Fri, 2019-06-21 at 07:08 -0700, Matt Roper wrote:
> > @@ -2912,18 +2920,19 @@ static void intel_ddi_clk_disable(struct
> > intel_encoder *encoder)
> > {
> > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > enum port port = encoder->port;
> > + enum phy phy = intel_port_to_phy(dev_priv, port);
> >
> > if (INTEL_GEN(dev_priv) >= 11) {
> > - if (!intel_port_is_combophy(dev_priv, port))
> > - I915_WRITE(DDI_CLK_SEL(port),
> > DDI_CLK_SEL_NONE);
> > + if (!intel_phy_is_combo(dev_priv, phy))
> > + I915_WRITE(DDI_CLK_SEL(phy), DDI_CLK_SEL_NONE);
>
>
> DDI_CLK_SEL() sets the clock to DDI so it should be port.
>
> Same for the registers bellow
I guess the rought guideline should be the register offset:
0x6Cxxx / 0x16xxxx -> phy
everything else -> port
or at least that's the impression I got from the quick read
of the spec.
--
Ville Syrjälä
Intel
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