On Fri, 2019-06-21 at 07:08 -0700, Matt Roper wrote:
> Our past DDI-based Intel platforms have had a fixed DDI<->PHY
> mapping.
> Because of this, both the bspec documentation and our i915 code has
> used
> the term "port" when talking about either DDI's or PHY's; it was
> always
> easy to tell what terms like "Port A" were referring to from the
> context.
>
> Unfortunately this is starting to break down now that EHL allows PHY-
> A
> to be driven by either DDI-A or DDI-D. Is a setup with DDI-D driving
> PHY-A considered "Port A" or "Port D?" The answer depends on which
> register we're working with, and even the bspec doesn't do a great
> job
> of clarifying this.
>
> Let's try to be more explicit about whether we're talking about the
> DDI
> or the PHY on gen11+ by using 'port' to refer to the DDI and creating
> a
> new 'enum phy' namespace to refer to the PHY in use.
>
> A few general notes:
>
> - ICL_PORT_COMP_* and ICL_PORT_CL_* belong to the actual combo PHY
> so
> they should always be programmed according to the PHY in use,
> regardless of which DDI is driving it.
>
> - The pipe part of the hardware expects "port" to refer to the
> DDI, so registers like TRANS_CLK_SEL and TRANS_DDI_FUNC_CTL should
> set bits according to the desired DDI (e.g., DDI-D) rather than
> the
> PHY (PHY-A).
>
> - Non-pipe registers refer to the PHY. Notably, DPCLKA_CFGCR0_ICL
> needs to set bits according to the PHY.
>
> Most of the changes here are on the combo PHY side. I didn't touch
> most
> of the TC port code yet, so it still refers to everything as ports.
> That's okay for now since there's no TC on EHL, but we'll probably
> want
> to separate out the DDI vs PHY terminology for TC in the future as
> well
> to avoid confusion.
>
> v2:
> - Convert a few more 'port' uses to 'phy.' (Sparse)
>
> Suggested-by: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: José Roberto de Souza <jose.souza@xxxxxxxxx>
> Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 24 ++-
> drivers/gpu/drm/i915/display/intel_bios.c | 4 +-
> .../gpu/drm/i915/display/intel_combo_phy.c | 143 +++++++++-------
> --
> .../gpu/drm/i915/display/intel_combo_phy.h | 3 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 106 +++++++------
> drivers/gpu/drm/i915/display/intel_display.c | 36 +++--
> drivers/gpu/drm/i915/display/intel_display.h | 16 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 12 +-
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 +-
> drivers/gpu/drm/i915/i915_reg.h | 18 +--
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> 11 files changed, 215 insertions(+), 159 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index b8673debf932..b338746003ea 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -365,10 +365,13 @@ static void gen11_dsi_power_up_lanes(struct
> intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> enum port port;
> + enum phy phy;
>
> - for_each_dsi_port(port, intel_dsi->ports)
> - intel_combo_phy_power_up_lanes(dev_priv, port, true,
> + for_each_dsi_port(port, intel_dsi->ports) {
> + phy = intel_port_to_phy(dev_priv, port);
> + intel_combo_phy_power_up_lanes(dev_priv, phy, true,
> intel_dsi->lane_count,
> false);
> + }
> }
>
> static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder
> *encoder)
> @@ -560,11 +563,13 @@ static void gen11_dsi_gate_clocks(struct
> intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + tmp |= DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -577,11 +582,13 @@ static void gen11_dsi_ungate_clocks(struct
> intel_encoder *encoder)
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> u32 tmp;
> enum port port;
> + enum phy phy;
>
> mutex_lock(&dev_priv->dpll_lock);
> tmp = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + tmp &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
>
> I915_WRITE(DPCLKA_CFGCR0_ICL, tmp);
> @@ -595,19 +602,22 @@ static void gen11_dsi_map_pll(struct
> intel_encoder *encoder,
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> enum port port;
> + enum phy phy;
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_dsi_port(port, intel_dsi->ports) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> + phy = intel_port_to_phy(dev_priv, port);
> + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + phy = intel_port_to_phy(dev_priv, port);
> + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c
> b/drivers/gpu/drm/i915/display/intel_bios.c
> index 0c9808132d67..4fdbb5c35d87 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -28,6 +28,7 @@
> #include <drm/drm_dp_helper.h>
> #include <drm/i915_drm.h>
>
> +#include "display/intel_display.h"
> #include "display/intel_gmbus.h"
>
> #include "i915_drv.h"
> @@ -1733,12 +1734,13 @@ init_vbt_missing_defaults(struct
> drm_i915_private *dev_priv)
> for (port = PORT_A; port < I915_MAX_PORTS; port++) {
> struct ddi_vbt_port_info *info =
> &dev_priv->vbt.ddi_port_info[port];
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> /*
> * VBT has the TypeC mode (native,TBT/USB) and we don't
> want
> * to detect it.
> */
> - if (intel_port_is_tc(dev_priv, port))
> + if (intel_phy_is_tc(dev_priv, phy))
> continue;
>
> info->supports_dvi = (port != PORT_A && port !=
> PORT_E);
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> index da590f1a998b..7b3047335d91 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.c
> @@ -6,13 +6,13 @@
> #include "intel_combo_phy.h"
> #include "intel_drv.h"
>
> -#define for_each_combo_port(__dev_priv, __port) \
> - for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
> \
> - for_each_if(intel_port_is_combophy(__dev_priv, __port))
> +#define for_each_combo_phy(__dev_priv, __phy) \
> + for ((__phy) = PHY_A; (__phy) < I915_MAX_PHYS; (__phy)++) \
> + for_each_if(intel_phy_is_combo(__dev_priv, __phy))
>
> -#define for_each_combo_port_reverse(__dev_priv, __port) \
> - for ((__port) = I915_MAX_PORTS; (__port)-- > PORT_A;) \
> - for_each_if(intel_port_is_combophy(__dev_priv, __port))
> +#define for_each_combo_phy_reverse(__dev_priv, __phy) \
> + for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
> + for_each_if(intel_phy_is_combo(__dev_priv, __phy))
>
> enum {
> PROCMON_0_85V_DOT_0,
> @@ -38,18 +38,17 @@ static const struct cnl_procmon {
> };
>
> /*
> - * CNL has just one set of registers, while ICL has two sets: one
> for port A and
> - * the other for port B. The CNL registers are equivalent to the ICL
> port A
> - * registers, that's why we call the ICL macros even though the
> function has CNL
> - * on its name.
> + * CNL has just one set of registers, while gen11 has a set for each
> combo PHY.
> + * The CNL registers are equivalent to the gen11 PHY A registers,
> that's why we
> + * call the ICL macros even though the function has CNL on its name.
> */
> static const struct cnl_procmon *
> -cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> port port)
> +cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum
> phy phy)
> {
> const struct cnl_procmon *procmon;
> u32 val;
>
> - val = I915_READ(ICL_PORT_COMP_DW3(port));
> + val = I915_READ(ICL_PORT_COMP_DW3(phy));
> switch (val & (PROCESS_INFO_MASK | VOLTAGE_INFO_MASK)) {
> default:
> MISSING_CASE(val);
> @@ -75,32 +74,32 @@ cnl_get_procmon_ref_values(struct
> drm_i915_private *dev_priv, enum port port)
> }
>
> static void cnl_set_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> const struct cnl_procmon *procmon;
> u32 val;
>
> - procmon = cnl_get_procmon_ref_values(dev_priv, port);
> + procmon = cnl_get_procmon_ref_values(dev_priv, phy);
>
> - val = I915_READ(ICL_PORT_COMP_DW1(port));
> + val = I915_READ(ICL_PORT_COMP_DW1(phy));
> val &= ~((0xff << 16) | 0xff);
> val |= procmon->dw1;
> - I915_WRITE(ICL_PORT_COMP_DW1(port), val);
> + I915_WRITE(ICL_PORT_COMP_DW1(phy), val);
>
> - I915_WRITE(ICL_PORT_COMP_DW9(port), procmon->dw9);
> - I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> + I915_WRITE(ICL_PORT_COMP_DW9(phy), procmon->dw9);
> + I915_WRITE(ICL_PORT_COMP_DW10(phy), procmon->dw10);
> }
>
> static bool check_phy_reg(struct drm_i915_private *dev_priv,
> - enum port port, i915_reg_t reg, u32 mask,
> + enum phy phy, i915_reg_t reg, u32 mask,
> u32 expected_val)
> {
> u32 val = I915_READ(reg);
>
> if ((val & mask) != expected_val) {
> - DRM_DEBUG_DRIVER("Port %c combo PHY reg %08x state
> mismatch: "
> + DRM_DEBUG_DRIVER("Combo PHY %c reg %08x state mismatch:
> "
> "current %08x mask %08x expected
> %08x\n",
> - port_name(port),
> + phy_name(phy),
> reg.reg, val, mask, expected_val);
> return false;
> }
> @@ -109,18 +108,18 @@ static bool check_phy_reg(struct
> drm_i915_private *dev_priv,
> }
>
> static bool cnl_verify_procmon_ref_values(struct drm_i915_private
> *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> const struct cnl_procmon *procmon;
> bool ret;
>
> - procmon = cnl_get_procmon_ref_values(dev_priv, port);
> + procmon = cnl_get_procmon_ref_values(dev_priv, phy);
>
> - ret = check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW1(port),
> + ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy),
> (0xff << 16) | 0xff, procmon->dw1);
> - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW9(port),
> + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy),
> -1U, procmon->dw9);
> - ret &= check_phy_reg(dev_priv, port, ICL_PORT_COMP_DW10(port),
> + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy),
> -1U, procmon->dw10);
>
> return ret;
> @@ -134,15 +133,15 @@ static bool cnl_combo_phy_enabled(struct
> drm_i915_private *dev_priv)
>
> static bool cnl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv)
> {
> - enum port port = PORT_A;
> + enum phy phy = PHY_A;
> bool ret;
>
> if (!cnl_combo_phy_enabled(dev_priv))
> return false;
>
> - ret = cnl_verify_procmon_ref_values(dev_priv, port);
> + ret = cnl_verify_procmon_ref_values(dev_priv, phy);
>
> - ret &= check_phy_reg(dev_priv, port, CNL_PORT_CL1CM_DW5,
> + ret &= check_phy_reg(dev_priv, phy, CNL_PORT_CL1CM_DW5,
> CL_POWER_DOWN_ENABLE,
> CL_POWER_DOWN_ENABLE);
>
> return ret;
> @@ -157,7 +156,7 @@ static void cnl_combo_phys_init(struct
> drm_i915_private *dev_priv)
> I915_WRITE(CHICKEN_MISC_2, val);
>
> /* Dummy PORT_A to get the correct CNL register from the ICL
> macro */
> - cnl_set_procmon_ref_values(dev_priv, PORT_A);
> + cnl_set_procmon_ref_values(dev_priv, PHY_A);
>
> val = I915_READ(CNL_PORT_COMP_DW0);
> val |= COMP_INIT;
> @@ -181,39 +180,39 @@ static void cnl_combo_phys_uninit(struct
> drm_i915_private *dev_priv)
> }
>
> static bool icl_combo_phy_enabled(struct drm_i915_private *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> /* The PHY C added by EHL has no PHY_MISC register */
> - if (port == PORT_C)
> - return I915_READ(ICL_PORT_COMP_DW0(port)) & COMP_INIT;
> + if (phy == PHY_C)
> + return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT;
> else
> - return !(I915_READ(ICL_PHY_MISC(port)) &
> + return !(I915_READ(ICL_PHY_MISC(phy)) &
> ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN) &&
> - (I915_READ(ICL_PORT_COMP_DW0(port)) &
> COMP_INIT);
> + (I915_READ(ICL_PORT_COMP_DW0(phy)) &
> COMP_INIT);
> }
>
> static bool icl_combo_phy_verify_state(struct drm_i915_private
> *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> bool ret;
>
> - if (!icl_combo_phy_enabled(dev_priv, port))
> + if (!icl_combo_phy_enabled(dev_priv, phy))
> return false;
>
> - ret = cnl_verify_procmon_ref_values(dev_priv, port);
> + ret = cnl_verify_procmon_ref_values(dev_priv, phy);
>
> - if (port == PORT_A)
> - ret &= check_phy_reg(dev_priv, port,
> ICL_PORT_COMP_DW8(port),
> + if (phy == PHY_A)
> + ret &= check_phy_reg(dev_priv, phy,
> ICL_PORT_COMP_DW8(phy),
> IREFGEN, IREFGEN);
>
> - ret &= check_phy_reg(dev_priv, port, ICL_PORT_CL_DW5(port),
> + ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy),
> CL_POWER_DOWN_ENABLE,
> CL_POWER_DOWN_ENABLE);
>
> return ret;
> }
>
> void intel_combo_phy_power_up_lanes(struct drm_i915_private
> *dev_priv,
> - enum port port, bool is_dsi,
> + enum phy phy, bool is_dsi,
> int lane_count, bool lane_reversal)
> {
> u8 lane_mask;
> @@ -258,10 +257,10 @@ void intel_combo_phy_power_up_lanes(struct
> drm_i915_private *dev_priv,
> }
> }
>
> - val = I915_READ(ICL_PORT_CL_DW10(port));
> + val = I915_READ(ICL_PORT_CL_DW10(phy));
> val &= ~PWR_DOWN_LN_MASK;
> val |= lane_mask << PWR_DOWN_LN_SHIFT;
> - I915_WRITE(ICL_PORT_CL_DW10(port), val);
> + I915_WRITE(ICL_PORT_CL_DW10(phy), val);
> }
>
> static u32 ehl_combo_phy_a_mux(struct drm_i915_private *i915, u32
> val)
> @@ -292,14 +291,14 @@ static u32 ehl_combo_phy_a_mux(struct
> drm_i915_private *i915, u32 val)
>
> static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
> {
> - enum port port;
> + enum phy phy;
>
> - for_each_combo_port(dev_priv, port) {
> + for_each_combo_phy(dev_priv, phy) {
> u32 val;
>
> - if (icl_combo_phy_verify_state(dev_priv, port)) {
> - DRM_DEBUG_DRIVER("Port %c combo PHY already
> enabled, won't reprogram it.\n",
> - port_name(port));
> + if (icl_combo_phy_verify_state(dev_priv, phy)) {
> + DRM_DEBUG_DRIVER("Combo PHY %c already enabled,
> won't reprogram it.\n",
> + phy_name(phy));
> continue;
> }
>
> @@ -308,7 +307,7 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
> * register for it and no need to program the
> * DE_IO_COMP_PWR_DOWN setting on PHY C.
> */
> - if (port != PORT_C) {
> + if (phy != PHY_C) {
> /*
> * EHL's combo PHY A can be hooked up to either
> an
> * external display (via DDI-D) or an internal
> display
> @@ -318,57 +317,57 @@ static void icl_combo_phys_init(struct
> drm_i915_private *dev_priv)
> * indicates the presence of any "internal"
> child
> * devices.
> */
> - val = I915_READ(ICL_PHY_MISC(port));
> - if (IS_ELKHARTLAKE(dev_priv) && port == PORT_A)
> + val = I915_READ(ICL_PHY_MISC(phy));
> + if (IS_ELKHARTLAKE(dev_priv) && phy == PHY_A)
> val = ehl_combo_phy_a_mux(dev_priv,
> val);
> val &= ~ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> - I915_WRITE(ICL_PHY_MISC(port), val);
> + I915_WRITE(ICL_PHY_MISC(phy), val);
> }
>
> - cnl_set_procmon_ref_values(dev_priv, port);
> + cnl_set_procmon_ref_values(dev_priv, phy);
>
> - if (port == PORT_A) {
> - val = I915_READ(ICL_PORT_COMP_DW8(port));
> + if (phy == PHY_A) {
> + val = I915_READ(ICL_PORT_COMP_DW8(phy));
> val |= IREFGEN;
> - I915_WRITE(ICL_PORT_COMP_DW8(port), val);
> + I915_WRITE(ICL_PORT_COMP_DW8(phy), val);
> }
>
> - val = I915_READ(ICL_PORT_COMP_DW0(port));
> + val = I915_READ(ICL_PORT_COMP_DW0(phy));
> val |= COMP_INIT;
> - I915_WRITE(ICL_PORT_COMP_DW0(port), val);
> + I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
>
> - val = I915_READ(ICL_PORT_CL_DW5(port));
> + val = I915_READ(ICL_PORT_CL_DW5(phy));
> val |= CL_POWER_DOWN_ENABLE;
> - I915_WRITE(ICL_PORT_CL_DW5(port), val);
> + I915_WRITE(ICL_PORT_CL_DW5(phy), val);
> }
> }
>
> static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
> {
> - enum port port;
> + enum phy phy;
>
> - for_each_combo_port_reverse(dev_priv, port) {
> + for_each_combo_phy_reverse(dev_priv, phy) {
> u32 val;
>
> - if (port == PORT_A &&
> - !icl_combo_phy_verify_state(dev_priv, port))
> - DRM_WARN("Port %c combo PHY HW state changed
> unexpectedly\n",
> - port_name(port));
> + if (phy == PHY_A &&
> + !icl_combo_phy_verify_state(dev_priv, phy))
> + DRM_WARN("Combo PHY %c HW state changed
> unexpectedly\n",
> + phy_name(phy));
>
> /*
> * Although EHL adds a combo PHY C, there's no PHY_MISC
> * register for it and no need to program the
> * DE_IO_COMP_PWR_DOWN setting on PHY C.
> */
> - if (port != PORT_C) {
> - val = I915_READ(ICL_PHY_MISC(port));
> + if (phy != PHY_C) {
> + val = I915_READ(ICL_PHY_MISC(phy));
> val |= ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN;
> - I915_WRITE(ICL_PHY_MISC(port), val);
> + I915_WRITE(ICL_PHY_MISC(phy), val);
> }
>
> - val = I915_READ(ICL_PORT_COMP_DW0(port));
> + val = I915_READ(ICL_PORT_COMP_DW0(phy));
> val &= ~COMP_INIT;
> - I915_WRITE(ICL_PORT_COMP_DW0(port), val);
> + I915_WRITE(ICL_PORT_COMP_DW0(phy), val);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_combo_phy.h
> b/drivers/gpu/drm/i915/display/intel_combo_phy.h
> index e6e195a83b19..80a1386b4c87 100644
> --- a/drivers/gpu/drm/i915/display/intel_combo_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_combo_phy.h
> @@ -10,11 +10,12 @@
> #include <drm/i915_drm.h>
>
> struct drm_i915_private;
> +enum phy;
>
> void intel_combo_phy_init(struct drm_i915_private *dev_priv);
> void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
> void intel_combo_phy_power_up_lanes(struct drm_i915_private
> *dev_priv,
> - enum port port, bool is_dsi,
> + enum phy phy, bool is_dsi,
> int lane_count, bool
> lane_reversal);
>
> #endif /* __INTEL_COMBO_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 593806d44ad4..06998198c648 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -867,11 +867,12 @@ icl_get_combo_buf_trans(struct drm_i915_private
> *dev_priv, int type, int rate,
> static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv,
> enum port port)
> {
> int n_entries, level, default_entry;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv,
> INTEL_OUTPUT_HDMI,
> 0, &n_entries);
> else
> @@ -1486,9 +1487,10 @@ static void icl_ddi_clock_get(struct
> intel_encoder *encoder,
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dpll_hw_state *pll_state = &pipe_config-
> >dpll_hw_state;
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int link_clock;
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);
> } else {
> enum intel_dpll_id pll_id =
> intel_get_shared_dpll_id(dev_priv,
> @@ -2085,6 +2087,7 @@ static void intel_ddi_get_power_domains(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> /*
> * TODO: Add support for MST encoders. Atm, the following
> should never
> @@ -2102,7 +2105,7 @@ static void intel_ddi_get_power_domains(struct
> intel_encoder *encoder,
> * ports.
> */
> if (intel_crtc_has_dp_encoder(crtc_state) ||
> - intel_port_is_tc(dev_priv, encoder->port))
> + intel_phy_is_tc(dev_priv, phy))
> intel_display_power_get(dev_priv,
> intel_ddi_main_link_aux_domain(
> dig_port));
>
> @@ -2227,10 +2230,11 @@ u8 intel_ddi_dp_voltage_max(struct
> intel_encoder *encoder)
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int n_entries;
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_get_combo_buf_trans(dev_priv, encoder-
> >type,
> intel_dp->link_rate,
> &n_entries);
> else
> @@ -2663,9 +2667,9 @@ static void icl_ddi_vswing_sequence(struct
> intel_encoder *encoder,
> enum intel_output_type type)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> - if (intel_port_is_combophy(dev_priv, port))
> + if (intel_phy_is_combo(dev_priv, phy))
> icl_combo_phy_ddi_vswing_sequence(encoder, level,
> type);
> else
> icl_mg_phy_ddi_vswing_sequence(encoder, link_clock,
> level);
> @@ -2728,12 +2732,13 @@ u32 ddi_signal_levels(struct intel_dp
> *intel_dp)
>
> static inline
> u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
> - enum port port)
> + enum phy phy)
> {
> - if (intel_port_is_combophy(dev_priv, port)) {
> - return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> - } else if (intel_port_is_tc(dev_priv, port)) {
> - enum tc_port tc_port = intel_port_to_tc(dev_priv,
> port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> + enum tc_port tc_port = intel_port_to_tc(dev_priv,
> + (enum
> port)phy);
>
> return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
> }
> @@ -2746,22 +2751,22 @@ static void icl_map_plls_to_ports(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> - WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, port)) ==
> 0);
> + WARN_ON((val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> + if (intel_phy_is_combo(dev_priv, phy)) {
> + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> POSTING_READ(DPCLKA_CFGCR0_ICL);
> }
>
> - val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -2770,13 +2775,13 @@ static void icl_map_plls_to_ports(struct
> intel_encoder *encoder,
> static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
> u32 val;
>
> mutex_lock(&dev_priv->dpll_lock);
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
>
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -2837,9 +2842,11 @@ void icl_sanitize_encoder_pll_mapping(struct
> intel_encoder *encoder)
>
> val = I915_READ(DPCLKA_CFGCR0_ICL);
> for_each_port_masked(port, port_mask) {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> +
> bool ddi_clk_ungated = !(val &
> icl_dpclka_cfgcr0_clk_off(dev_
> priv,
> - port
> ));
> + phy)
> );
>
> if (ddi_clk_needed == ddi_clk_ungated)
> continue;
> @@ -2851,9 +2858,9 @@ void icl_sanitize_encoder_pll_mapping(struct
> intel_encoder *encoder)
> if (WARN_ON(ddi_clk_needed))
> continue;
>
> - DRM_NOTE("Port %c is disabled/in DSI mode with an
> ungated DDI clock, gate it\n",
> - port_name(port));
> - val |= icl_dpclka_cfgcr0_clk_off(dev_priv, port);
> + DRM_NOTE("PHY %c is disabled/in DSI mode with an
> ungated DDI clock, gate it\n",
> + phy_name(port));
> + val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
> I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> }
> }
> @@ -2863,6 +2870,7 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> u32 val;
> const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
>
> @@ -2872,14 +2880,14 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
> mutex_lock(&dev_priv->dpll_lock);
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (!intel_port_is_combophy(dev_priv, port))
> - I915_WRITE(DDI_CLK_SEL(port),
> + if (!intel_phy_is_combo(dev_priv, phy))
> + I915_WRITE(DDI_CLK_SEL(phy),
> icl_pll_to_ddi_clk_sel(encoder,
> crtc_state));
> } else if (IS_CANNONLAKE(dev_priv)) {
> /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI.
> */
> val = I915_READ(DPCLKA_CFGCR0);
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> + val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> I915_WRITE(DPCLKA_CFGCR0, val);
>
> /*
> @@ -2888,21 +2896,21 @@ static void intel_ddi_clk_select(struct
> intel_encoder *encoder,
> * register writes.
> */
> val = I915_READ(DPCLKA_CFGCR0);
> - val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> + val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> I915_WRITE(DPCLKA_CFGCR0, val);
> } else if (IS_GEN9_BC(dev_priv)) {
> /* DDI -> PLL mapping */
> val = I915_READ(DPLL_CTRL2);
>
> - val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
> - DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
> - val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
> - DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
> + val &= ~(DPLL_CTRL2_DDI_CLK_OFF(phy) |
> + DPLL_CTRL2_DDI_CLK_SEL_MASK(phy));
> + val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, phy) |
> + DPLL_CTRL2_DDI_SEL_OVERRIDE(phy));
>
> I915_WRITE(DPLL_CTRL2, val);
>
> } else if (INTEL_GEN(dev_priv) < 9) {
> - I915_WRITE(PORT_CLK_SEL(port),
> hsw_pll_to_ddi_pll_sel(pll));
> + I915_WRITE(PORT_CLK_SEL(phy),
> hsw_pll_to_ddi_pll_sel(pll));
> }
>
> mutex_unlock(&dev_priv->dpll_lock);
> @@ -2912,18 +2920,19 @@ static void intel_ddi_clk_disable(struct
> intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> if (INTEL_GEN(dev_priv) >= 11) {
> - if (!intel_port_is_combophy(dev_priv, port))
> - I915_WRITE(DDI_CLK_SEL(port),
> DDI_CLK_SEL_NONE);
> + if (!intel_phy_is_combo(dev_priv, phy))
> + I915_WRITE(DDI_CLK_SEL(phy), DDI_CLK_SEL_NONE);
DDI_CLK_SEL() sets the clock to DDI so it should be port.
Same for the registers bellow
> } else if (IS_CANNONLAKE(dev_priv)) {
> I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
> - DPCLKA_CFGCR0_DDI_CLK_OFF(port));
> + DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
> } else if (IS_GEN9_BC(dev_priv)) {
> I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
> - DPLL_CTRL2_DDI_CLK_OFF(port));
> + DPLL_CTRL2_DDI_CLK_OFF(phy));
> } else if (INTEL_GEN(dev_priv) < 9) {
> - I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
> + I915_WRITE(PORT_CLK_SEL(phy), PORT_CLK_SEL_NONE);
> }
> }
>
> @@ -3110,6 +3119,7 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> bool is_mst = intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_DP_MST);
> int level = intel_ddi_dp_level(intel_dp);
> @@ -3138,11 +3148,11 @@ static void intel_ddi_pre_enable_dp(struct
> intel_encoder *encoder,
> else
> intel_prepare_dp_ddi_buffers(encoder, crtc_state);
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> bool lane_reversal =
> dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL;
>
> - intel_combo_phy_power_up_lanes(dev_priv, port, false,
> + intel_combo_phy_power_up_lanes(dev_priv, phy, false,
> crtc_state->lane_count,
> lane_reversal);
> }
> @@ -3630,7 +3640,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder
> *encoder,
> enum port port = encoder->port;
>
> if (intel_crtc_has_dp_encoder(crtc_state) ||
> - intel_port_is_tc(dev_priv, encoder->port))
> + intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> port)))
> intel_display_power_get(dev_priv,
> intel_ddi_main_link_aux_domain(
> dig_port));
>
> @@ -3656,9 +3666,10 @@ intel_ddi_post_pll_disable(struct
> intel_encoder *encoder,
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> if (intel_crtc_has_dp_encoder(crtc_state) ||
> - intel_port_is_tc(dev_priv, encoder->port))
> + intel_phy_is_tc(dev_priv, phy))
> intel_display_power_put_unchecked(dev_priv,
> intel_ddi_main_link_a
> ux_domain(dig_port));
> }
> @@ -3934,8 +3945,9 @@ static void intel_ddi_encoder_reset(struct
> drm_encoder *drm_encoder)
> {
> struct intel_digital_port *dig_port =
> enc_to_dig_port(drm_encoder);
> struct drm_i915_private *i915 = to_i915(drm_encoder->dev);
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>
> - if (intel_port_is_tc(i915, dig_port->base.port))
> + if (intel_phy_is_tc(i915, phy))
> intel_digital_port_connected(&dig_port->base);
>
> intel_dp_encoder_reset(drm_encoder);
> @@ -3945,10 +3957,11 @@ static void intel_ddi_encoder_destroy(struct
> drm_encoder *encoder)
> {
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> struct drm_i915_private *i915 = to_i915(encoder->dev);
> + enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
>
> intel_dp_encoder_flush_work(encoder);
>
> - if (intel_port_is_tc(i915, dig_port->base.port))
> + if (intel_phy_is_tc(i915, phy))
> icl_tc_phy_disconnect(i915, dig_port);
>
> drm_encoder_cleanup(encoder);
> @@ -4198,6 +4211,7 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> struct drm_encoder *encoder;
> bool init_hdmi, init_dp, init_lspcon = false;
> enum pipe pipe;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> init_hdmi = port_info->supports_dvi || port_info-
> >supports_hdmi;
> init_dp = port_info->supports_dp;
> @@ -4261,7 +4275,7 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> intel_dig_port->max_lanes =
> intel_ddi_max_lanes(intel_dig_port);
> intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv,
> port);
>
> - intel_dig_port->tc_legacy_port = intel_port_is_tc(dev_priv,
> port) &&
> + intel_dig_port->tc_legacy_port = intel_phy_is_tc(dev_priv, phy)
> &&
> !port_info->supports_typec_usb
> &&
> !port_info->supports_tbt;
>
> @@ -4324,7 +4338,7 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
>
> intel_infoframe_init(intel_dig_port);
>
> - if (intel_port_is_tc(dev_priv, port))
> + if (intel_phy_is_tc(dev_priv, phy))
> intel_digital_port_connected(intel_encoder);
>
> return;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 8592a7d422de..e72ace42327c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6560,31 +6560,39 @@ static void i9xx_pfit_enable(const struct
> intel_crtc_state *crtc_state)
> I915_WRITE(BCLRPAT(crtc->pipe), 0);
> }
>
> -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port)
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy)
> {
> - if (port == PORT_NONE)
> + if (phy == PHY_NONE)
> return false;
>
> if (IS_ELKHARTLAKE(dev_priv))
> - return port <= PORT_C;
> + return phy <= PHY_C;
>
> if (INTEL_GEN(dev_priv) >= 11)
> - return port <= PORT_B;
> + return phy <= PHY_B;
>
> return false;
> }
>
> -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port)
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy)
> {
> if (INTEL_GEN(dev_priv) >= 11 && !IS_ELKHARTLAKE(dev_priv))
> - return port >= PORT_C && port <= PORT_F;
> + return phy >= PHY_C && phy <= PHY_F;
>
> return false;
> }
>
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port
> port)
> +{
> + if (IS_ELKHARTLAKE(i915) && port == PORT_D)
> + return PHY_A;
> +
> + return (enum phy)port;
> +}
> +
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port)
> {
> - if (!intel_port_is_tc(dev_priv, port))
> + if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> port)))
> return PORT_TC_NONE;
>
> return port - PORT_C;
> @@ -9922,9 +9930,10 @@ static void cannonlake_get_ddi_pll(struct
> drm_i915_private *dev_priv,
> {
> enum intel_dpll_id id;
> u32 temp;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
>
> - temp = I915_READ(DPCLKA_CFGCR0) &
> DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> + temp = I915_READ(DPCLKA_CFGCR0) &
> DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
Should be port, same for the icelake_get_ddi_pll()
>
> if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2))
> return;
> @@ -9936,15 +9945,16 @@ static void icelake_get_ddi_pll(struct
> drm_i915_private *dev_priv,
> enum port port,
> struct intel_crtc_state *pipe_config)
> {
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> enum intel_dpll_id id;
> u32 temp;
>
> /* TODO: TBT pll not implemented. */
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> temp = I915_READ(DPCLKA_CFGCR0_ICL) &
> - DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
> - id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port);
> - } else if (intel_port_is_tc(dev_priv, port)) {
> + DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> + id = temp >> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
> port));
> } else {
> WARN(1, "Invalid port %x\n", port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h
> b/drivers/gpu/drm/i915/display/intel_display.h
> index ee6b8194a459..f89b0b779f18 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -229,6 +229,21 @@ struct intel_link_m_n {
> u32 link_n;
> };
>
> +enum phy {
> + PHY_NONE = -1,
> +
> + PHY_A = 0,
> + PHY_B,
> + PHY_C,
> + PHY_D,
> + PHY_E,
> + PHY_F,
> +
> + I915_MAX_PHYS
> +};
> +
> +#define phy_name(a) ((a) + 'A')
> +
> #define for_each_pipe(__dev_priv, __p) \
> for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes;
> (__p)++)
>
> @@ -357,5 +372,6 @@ void lpt_disable_clkout_dp(struct
> drm_i915_private *dev_priv);
> u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier);
> bool intel_plane_can_remap(const struct intel_plane_state
> *plane_state);
> +enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port
> port);
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4336df46fe78..577538132a80 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -329,9 +329,9 @@ static int icl_max_source_rate(struct intel_dp
> *intel_dp)
> {
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = to_i915(dig_port-
> >base.base.dev);
> - enum port port = dig_port->base.port;
> + enum phy phy = intel_port_to_phy(dev_priv, dig_port-
> >base.port);
>
> - if (intel_port_is_combophy(dev_priv, port) &&
> + if (intel_phy_is_combo(dev_priv, phy) &&
> !IS_ELKHARTLAKE(dev_priv) &&
> !intel_dp_is_edp(intel_dp))
> return 540000;
> @@ -5425,10 +5425,11 @@ static bool icl_digital_port_connected(struct
> intel_encoder *encoder)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> + enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
>
> - if (intel_port_is_combophy(dev_priv, encoder->port))
> + if (intel_phy_is_combo(dev_priv, phy))
> return icl_combo_port_connected(dev_priv, dig_port);
> - else if (intel_port_is_tc(dev_priv, encoder->port))
> + else if (intel_phy_is_tc(dev_priv, phy))
> return icl_tc_port_connected(dev_priv, dig_port);
> else
> MISSING_CASE(encoder->hpd_pin);
> @@ -7332,6 +7333,7 @@ intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
> struct drm_device *dev = intel_encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = intel_encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> int type;
>
> /* Initialize the work for modeset in case of link train
> failure */
> @@ -7358,7 +7360,7 @@ intel_dp_init_connector(struct
> intel_digital_port *intel_dig_port,
> * Currently we don't support eDP on TypeC ports,
> although in
> * theory it could work on TypeC legacy ports.
> */
> - WARN_ON(intel_port_is_tc(dev_priv, port));
> + WARN_ON(intel_phy_is_tc(dev_priv, phy));
> type = DRM_MODE_CONNECTOR_eDP;
> } else {
> type = DRM_MODE_CONNECTOR_DisplayPort;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 2d4e7b9a7b9d..7bf697848055 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2513,7 +2513,8 @@ static bool icl_calc_dpll_state(struct
> intel_crtc_state *crtc_state,
> struct skl_wrpll_params pll_params = { 0 };
> bool ret;
>
> - if (intel_port_is_tc(dev_priv, encoder->port))
> + if (intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv,
> + encoder-
> >port)))
> ret = icl_calc_tbt_pll(crtc_state, &pll_params);
> else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> @@ -2800,14 +2801,15 @@ icl_get_dpll(struct intel_crtc_state
> *crtc_state,
> struct intel_digital_port *intel_dig_port;
> struct intel_shared_dpll *pll;
> enum port port = encoder->port;
> + enum phy phy = intel_port_to_phy(dev_priv, port);
> enum intel_dpll_id min, max;
> bool ret;
>
> - if (intel_port_is_combophy(dev_priv, port)) {
> + if (intel_phy_is_combo(dev_priv, phy)) {
> min = DPLL_ID_ICL_DPLL0;
> max = DPLL_ID_ICL_DPLL1;
> ret = icl_calc_dpll_state(crtc_state, encoder);
> - } else if (intel_port_is_tc(dev_priv, port)) {
> + } else if (intel_phy_is_tc(dev_priv, phy)) {
> if (encoder->type == INTEL_OUTPUT_DP_MST) {
> struct intel_dp_mst_encoder *mst_encoder;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 7e748bb3f324..2a557895ec71 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1794,12 +1794,12 @@ enum i915_power_well_id {
> #define _ICL_COMBOPHY_A 0x162000
> #define _ICL_COMBOPHY_B 0x6C000
> #define _ICL_COMBOPHY_C_EHL 0x160000
> -#define _ICL_COMBOPHY(port) _PICK(port, _ICL_COMBOPHY_A, \
> +#define _ICL_COMBOPHY(phy) _PICK(phy, _ICL_COMBOPHY_A, \
> _ICL_COMBOPHY_B, \
> _ICL_COMBOPHY_C_EHL)
>
> /* CNL/ICL Port CL_DW registers */
> -#define _ICL_PORT_CL_DW(dw, port) (_ICL_COMBOPHY(port) + \
> +#define _ICL_PORT_CL_DW(dw, phy) (_ICL_COMBOPHY(phy) + \
> 4 * (dw))
>
> #define CNL_PORT_CL1CM_DW5 _MMIO(0x162014)
> @@ -9681,15 +9681,15 @@ enum skl_power_gate {
> */
> #define DPCLKA_CFGCR0 _MMIO(0x6C200)
> #define DPCLKA_CFGCR0_ICL _MMIO(0x164280)
> -#define DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port)
> == PORT_F ? 23 : \
> - (port) + 10))
> -#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) + 10))
> +#define DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << ((phy) ==
> PHY_F ? 23 : \
> + (phy) + 10))
> +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy) (1 << _PICK(phy, 10,
> 11, 25))
> #define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) ==
> PORT_TC4 ? \
> 21 : (tc_port) +
> 12))
> -#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port) ((port) ==
> PORT_F ? 21 : \
> - (port) * 2)
> -#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port) (3 <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> -#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port) ((pll) <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))
> +#define DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy) ((phy) == PHY_F
> ? 21 : \
> + (phy) * 2)
> +#define DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy) (3 <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
> +#define DPCLKA_CFGCR0_DDI_CLK_SEL(pll, phy) ((pll) <<
> DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
>
> /* CNL PLL */
> #define DPLL0_ENABLE 0x46010
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 1d58f7ec5d84..8c174bb767ba 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1473,8 +1473,8 @@ void intel_pps_unlock_regs_wa(struct
> drm_i915_private *dev_priv);
> void intel_encoder_destroy(struct drm_encoder *encoder);
> struct drm_display_mode *
> intel_encoder_current_mode(struct intel_encoder *encoder);
> -bool intel_port_is_combophy(struct drm_i915_private *dev_priv, enum
> port port);
> -bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port
> port);
> +bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy
> phy);
> +bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy
> phy);
> enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
> enum port port);
> int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void
> *data,
Other than those above looks good but as this is a big change would be
nice to have another set of eyes reviewing.
+ Imre Deak <imre.deak@xxxxxxxxx>
This will conflict with this type-c/TBT patches and he worked in combo
phy changes recently.
+ Ville and Jani
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