On Fri, May 03, 2019 at 10:31:43PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> hsw_enable_pc8()/hsw_disable_pc8() are more less equivalent to
> the display core init/unit functions of later platforms. Relocate
> the hsw/bdw code into intel_runtime_pm.c so that it sits next to
> its cousins.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 222 +----------------------
> drivers/gpu/drm/i915/intel_display.h | 4 +
> drivers/gpu/drm/i915/intel_drv.h | 2 -
> drivers/gpu/drm/i915/intel_runtime_pm.c | 223 ++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_runtime_pm.h | 2 +
> 5 files changed, 230 insertions(+), 223 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d81ec80e34f6..a351c8e219ba 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8725,7 +8725,7 @@ static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
> }
>
> /* Sequence to disable CLKOUT_DP */
> -static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
> +void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
> {
> u32 reg, tmp;
>
> @@ -9482,226 +9482,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
>
> return ret;
> }
> -
> -static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> -{
> - struct drm_device *dev = &dev_priv->drm;
> - struct intel_crtc *crtc;
> -
> - for_each_intel_crtc(dev, crtc)
> - I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
> - pipe_name(crtc->pipe));
> -
> - I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
> - "Display power well on\n");
> - I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
> - I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
> - I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
> - I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
> - I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> - "CPU PWM1 enabled\n");
> - if (IS_HASWELL(dev_priv))
> - I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
> - "CPU PWM2 enabled\n");
> - I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
> - "PCH PWM1 enabled\n");
> - I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
> - "Utility pin enabled\n");
> - I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
> -
> - /*
> - * In theory we can still leave IRQs enabled, as long as only the HPD
> - * interrupts remain enabled. We used to check for that, but since it's
> - * gen-specific and since we only disable LCPLL after we fully disable
> - * the interrupts, the check below should be enough.
> - */
> - I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
> -}
> -
> -static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
> -{
> - if (IS_HASWELL(dev_priv))
> - return I915_READ(D_COMP_HSW);
> - else
> - return I915_READ(D_COMP_BDW);
> -}
> -
> -static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
> -{
> - if (IS_HASWELL(dev_priv)) {
> - if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
> - val))
> - DRM_DEBUG_KMS("Failed to write to D_COMP\n");
> - } else {
> - I915_WRITE(D_COMP_BDW, val);
> - POSTING_READ(D_COMP_BDW);
> - }
> -}
> -
> -/*
> - * This function implements pieces of two sequences from BSpec:
> - * - Sequence for display software to disable LCPLL
> - * - Sequence for display software to allow package C8+
> - * The steps implemented here are just the steps that actually touch the LCPLL
> - * register. Callers should take care of disabling all the display engine
> - * functions, doing the mode unset, fixing interrupts, etc.
> - */
> -static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
> - bool switch_to_fclk, bool allow_power_down)
> -{
> - u32 val;
> -
> - assert_can_disable_lcpll(dev_priv);
> -
> - val = I915_READ(LCPLL_CTL);
> -
> - if (switch_to_fclk) {
> - val |= LCPLL_CD_SOURCE_FCLK;
> - I915_WRITE(LCPLL_CTL, val);
> -
> - if (wait_for_us(I915_READ(LCPLL_CTL) &
> - LCPLL_CD_SOURCE_FCLK_DONE, 1))
> - DRM_ERROR("Switching to FCLK failed\n");
> -
> - val = I915_READ(LCPLL_CTL);
> - }
> -
> - val |= LCPLL_PLL_DISABLE;
> - I915_WRITE(LCPLL_CTL, val);
> - POSTING_READ(LCPLL_CTL);
> -
> - if (intel_wait_for_register(&dev_priv->uncore,
> - LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
> - DRM_ERROR("LCPLL still locked\n");
> -
> - val = hsw_read_dcomp(dev_priv);
> - val |= D_COMP_COMP_DISABLE;
> - hsw_write_dcomp(dev_priv, val);
> - ndelay(100);
> -
> - if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
> - 1))
> - DRM_ERROR("D_COMP RCOMP still in progress\n");
> -
> - if (allow_power_down) {
> - val = I915_READ(LCPLL_CTL);
> - val |= LCPLL_POWER_DOWN_ALLOW;
> - I915_WRITE(LCPLL_CTL, val);
> - POSTING_READ(LCPLL_CTL);
> - }
> -}
> -
> -/*
> - * Fully restores LCPLL, disallowing power down and switching back to LCPLL
> - * source.
> - */
> -static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> -{
> - u32 val;
> -
> - val = I915_READ(LCPLL_CTL);
> -
> - if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
> - LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
> - return;
> -
> - /*
> - * Make sure we're not on PC8 state before disabling PC8, otherwise
> - * we'll hang the machine. To prevent PC8 state, just enable force_wake.
> - */
> - intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> -
> - if (val & LCPLL_POWER_DOWN_ALLOW) {
> - val &= ~LCPLL_POWER_DOWN_ALLOW;
> - I915_WRITE(LCPLL_CTL, val);
> - POSTING_READ(LCPLL_CTL);
> - }
> -
> - val = hsw_read_dcomp(dev_priv);
> - val |= D_COMP_COMP_FORCE;
> - val &= ~D_COMP_COMP_DISABLE;
> - hsw_write_dcomp(dev_priv, val);
> -
> - val = I915_READ(LCPLL_CTL);
> - val &= ~LCPLL_PLL_DISABLE;
> - I915_WRITE(LCPLL_CTL, val);
> -
> - if (intel_wait_for_register(&dev_priv->uncore,
> - LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
> - 5))
> - DRM_ERROR("LCPLL not locked yet\n");
> -
> - if (val & LCPLL_CD_SOURCE_FCLK) {
> - val = I915_READ(LCPLL_CTL);
> - val &= ~LCPLL_CD_SOURCE_FCLK;
> - I915_WRITE(LCPLL_CTL, val);
> -
> - if (wait_for_us((I915_READ(LCPLL_CTL) &
> - LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
> - DRM_ERROR("Switching back to LCPLL failed\n");
> - }
> -
> - intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> -
> - intel_update_cdclk(dev_priv);
> - intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> -}
> -
> -/*
> - * Package states C8 and deeper are really deep PC states that can only be
> - * reached when all the devices on the system allow it, so even if the graphics
> - * device allows PC8+, it doesn't mean the system will actually get to these
> - * states. Our driver only allows PC8+ when going into runtime PM.
> - *
> - * The requirements for PC8+ are that all the outputs are disabled, the power
> - * well is disabled and most interrupts are disabled, and these are also
> - * requirements for runtime PM. When these conditions are met, we manually do
> - * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
> - * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
> - * hang the machine.
> - *
> - * When we really reach PC8 or deeper states (not just when we allow it) we lose
> - * the state of some registers, so when we come back from PC8+ we need to
> - * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
> - * need to take care of the registers kept by RC6. Notice that this happens even
> - * if we don't put the device in PCI D3 state (which is what currently happens
> - * because of the runtime PM support).
> - *
> - * For more, read "Display Sequences for Package C8" on the hardware
> - * documentation.
> - */
> -void hsw_enable_pc8(struct drm_i915_private *dev_priv)
> -{
> - u32 val;
> -
> - DRM_DEBUG_KMS("Enabling package C8+\n");
> -
> - if (HAS_PCH_LPT_LP(dev_priv)) {
> - val = I915_READ(SOUTH_DSPCLK_GATE_D);
> - val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> - I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> - }
> -
> - lpt_disable_clkout_dp(dev_priv);
> - hsw_disable_lcpll(dev_priv, true, true);
> -}
> -
> -void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> -{
> - u32 val;
> -
> - DRM_DEBUG_KMS("Disabling package C8+\n");
> -
> - hsw_restore_lcpll(dev_priv);
> - lpt_init_pch_refclk(dev_priv);
> -
> - if (HAS_PCH_LPT_LP(dev_priv)) {
> - val = I915_READ(SOUTH_DSPCLK_GATE_D);
> - val |= PCH_LP_PARTITION_LEVEL_DISABLE;
> - I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> - }
> -}
> -
> static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
> struct intel_crtc_state *crtc_state)
> {
> diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
> index 2220588e86ac..1b6f5a71184d 100644
> --- a/drivers/gpu/drm/i915/intel_display.h
> +++ b/drivers/gpu/drm/i915/intel_display.h
> @@ -28,6 +28,8 @@
> #include <drm/drm_util.h>
> #include <drm/i915_drm.h>
>
> +struct drm_i915_private;
> +
> enum i915_gpio {
> GPIOA,
> GPIOB,
> @@ -432,4 +434,6 @@ void intel_link_compute_m_n(u16 bpp, int nlanes,
> struct intel_link_m_n *m_n,
> bool constant_n);
> bool is_ccs_modifier(u64 modifier);
> +void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv);
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 4049e03d2c0d..247893ed1543 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1571,8 +1571,6 @@ void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> void intel_prepare_reset(struct drm_i915_private *dev_priv);
> void intel_finish_reset(struct drm_i915_private *dev_priv);
> -void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> -void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> unsigned int skl_cdclk_get_vco(unsigned int freq);
> void intel_dp_get_m_n(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index b1fd2ae99199..b8fadd1b685c 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3642,6 +3642,229 @@ static void hsw_assert_cdclk(struct drm_i915_private *dev_priv)
> DRM_ERROR("LCPLL is disabled\n");
> }
>
> +static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
> +{
> + struct drm_device *dev = &dev_priv->drm;
> + struct intel_crtc *crtc;
> +
> + for_each_intel_crtc(dev, crtc)
> + I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
> + pipe_name(crtc->pipe));
> +
> + I915_STATE_WARN(I915_READ(HSW_PWR_WELL_CTL2),
> + "Display power well on\n");
> + I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE,
> + "SPLL enabled\n");
> + I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE,
> + "WRPLL1 enabled\n");
> + I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE,
> + "WRPLL2 enabled\n");
> + I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON,
> + "Panel power on\n");
> + I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
> + "CPU PWM1 enabled\n");
> + if (IS_HASWELL(dev_priv))
> + I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
> + "CPU PWM2 enabled\n");
> + I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
> + "PCH PWM1 enabled\n");
> + I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
> + "Utility pin enabled\n");
> + I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE,
> + "PCH GTC enabled\n");
> +
> + /*
> + * In theory we can still leave IRQs enabled, as long as only the HPD
> + * interrupts remain enabled. We used to check for that, but since it's
> + * gen-specific and since we only disable LCPLL after we fully disable
> + * the interrupts, the check below should be enough.
> + */
> + I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
> +}
> +
> +static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
> +{
> + if (IS_HASWELL(dev_priv))
> + return I915_READ(D_COMP_HSW);
> + else
> + return I915_READ(D_COMP_BDW);
> +}
> +
> +static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
> +{
> + if (IS_HASWELL(dev_priv)) {
> + if (sandybridge_pcode_write(dev_priv,
> + GEN6_PCODE_WRITE_D_COMP, val))
> + DRM_DEBUG_KMS("Failed to write to D_COMP\n");
> + } else {
> + I915_WRITE(D_COMP_BDW, val);
> + POSTING_READ(D_COMP_BDW);
> + }
> +}
> +
> +/*
> + * This function implements pieces of two sequences from BSpec:
> + * - Sequence for display software to disable LCPLL
> + * - Sequence for display software to allow package C8+
> + * The steps implemented here are just the steps that actually touch the LCPLL
> + * register. Callers should take care of disabling all the display engine
> + * functions, doing the mode unset, fixing interrupts, etc.
> + */
> +static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
> + bool switch_to_fclk, bool allow_power_down)
> +{
> + u32 val;
> +
> + assert_can_disable_lcpll(dev_priv);
> +
> + val = I915_READ(LCPLL_CTL);
> +
> + if (switch_to_fclk) {
> + val |= LCPLL_CD_SOURCE_FCLK;
> + I915_WRITE(LCPLL_CTL, val);
> +
> + if (wait_for_us(I915_READ(LCPLL_CTL) &
> + LCPLL_CD_SOURCE_FCLK_DONE, 1))
> + DRM_ERROR("Switching to FCLK failed\n");
> +
> + val = I915_READ(LCPLL_CTL);
> + }
> +
> + val |= LCPLL_PLL_DISABLE;
> + I915_WRITE(LCPLL_CTL, val);
> + POSTING_READ(LCPLL_CTL);
> +
> + if (intel_wait_for_register(&dev_priv->uncore, LCPLL_CTL,
> + LCPLL_PLL_LOCK, 0, 1))
> + DRM_ERROR("LCPLL still locked\n");
> +
> + val = hsw_read_dcomp(dev_priv);
> + val |= D_COMP_COMP_DISABLE;
> + hsw_write_dcomp(dev_priv, val);
> + ndelay(100);
> +
> + if (wait_for((hsw_read_dcomp(dev_priv) &
> + D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
> + DRM_ERROR("D_COMP RCOMP still in progress\n");
> +
> + if (allow_power_down) {
> + val = I915_READ(LCPLL_CTL);
> + val |= LCPLL_POWER_DOWN_ALLOW;
> + I915_WRITE(LCPLL_CTL, val);
> + POSTING_READ(LCPLL_CTL);
> + }
> +}
> +
> +/*
> + * Fully restores LCPLL, disallowing power down and switching back to LCPLL
> + * source.
> + */
> +static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + val = I915_READ(LCPLL_CTL);
> +
> + if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
> + LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
> + return;
> +
> + /*
> + * Make sure we're not on PC8 state before disabling PC8, otherwise
> + * we'll hang the machine. To prevent PC8 state, just enable force_wake.
> + */
> + intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
> +
> + if (val & LCPLL_POWER_DOWN_ALLOW) {
> + val &= ~LCPLL_POWER_DOWN_ALLOW;
> + I915_WRITE(LCPLL_CTL, val);
> + POSTING_READ(LCPLL_CTL);
> + }
> +
> + val = hsw_read_dcomp(dev_priv);
> + val |= D_COMP_COMP_FORCE;
> + val &= ~D_COMP_COMP_DISABLE;
> + hsw_write_dcomp(dev_priv, val);
> +
> + val = I915_READ(LCPLL_CTL);
> + val &= ~LCPLL_PLL_DISABLE;
> + I915_WRITE(LCPLL_CTL, val);
> +
> + if (intel_wait_for_register(&dev_priv->uncore, LCPLL_CTL,
> + LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, 5))
> + DRM_ERROR("LCPLL not locked yet\n");
> +
> + if (val & LCPLL_CD_SOURCE_FCLK) {
> + val = I915_READ(LCPLL_CTL);
> + val &= ~LCPLL_CD_SOURCE_FCLK;
> + I915_WRITE(LCPLL_CTL, val);
> +
> + if (wait_for_us((I915_READ(LCPLL_CTL) &
> + LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
> + DRM_ERROR("Switching back to LCPLL failed\n");
> + }
> +
> + intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
> +
> + intel_update_cdclk(dev_priv);
> + intel_dump_cdclk_state(&dev_priv->cdclk.hw, "Current CDCLK");
> +}
> +
> +/*
> + * Package states C8 and deeper are really deep PC states that can only be
> + * reached when all the devices on the system allow it, so even if the graphics
> + * device allows PC8+, it doesn't mean the system will actually get to these
> + * states. Our driver only allows PC8+ when going into runtime PM.
> + *
> + * The requirements for PC8+ are that all the outputs are disabled, the power
> + * well is disabled and most interrupts are disabled, and these are also
> + * requirements for runtime PM. When these conditions are met, we manually do
> + * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
> + * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
> + * hang the machine.
> + *
> + * When we really reach PC8 or deeper states (not just when we allow it) we lose
> + * the state of some registers, so when we come back from PC8+ we need to
> + * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
> + * need to take care of the registers kept by RC6. Notice that this happens even
> + * if we don't put the device in PCI D3 state (which is what currently happens
> + * because of the runtime PM support).
> + *
> + * For more, read "Display Sequences for Package C8" on the hardware
> + * documentation.
> + */
> +void hsw_enable_pc8(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + DRM_DEBUG_KMS("Enabling package C8+\n");
> +
> + if (HAS_PCH_LPT_LP(dev_priv)) {
> + val = I915_READ(SOUTH_DSPCLK_GATE_D);
> + val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> + }
> +
> + lpt_disable_clkout_dp(dev_priv);
> + hsw_disable_lcpll(dev_priv, true, true);
> +}
> +
> +void hsw_disable_pc8(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + DRM_DEBUG_KMS("Disabling package C8+\n");
> +
> + hsw_restore_lcpll(dev_priv);
> + intel_init_pch_refclk(dev_priv);
> +
> + if (HAS_PCH_LPT_LP(dev_priv)) {
> + val = I915_READ(SOUTH_DSPCLK_GATE_D);
> + val |= PCH_LP_PARTITION_LEVEL_DISABLE;
> + I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
> + }
> +}
> +
> static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv,
> bool enable)
> {
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
> index 69227756de3e..e30b38632bd2 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.h
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
> @@ -37,6 +37,8 @@ void intel_power_domains_disable(struct drm_i915_private *dev_priv);
> void intel_power_domains_suspend(struct drm_i915_private *dev_priv,
> enum i915_drm_suspend_mode);
> void intel_power_domains_resume(struct drm_i915_private *dev_priv);
> +void hsw_enable_pc8(struct drm_i915_private *dev_priv);
> +void hsw_disable_pc8(struct drm_i915_private *dev_priv);
> void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
> void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
> --
> 2.21.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
