No functional change. But by making those bits together
we will be able to convert many functions to pass
intel_irq instead of i915_private or uncore.
For gen8+ "gt_" prefix would be better than pm_ on them
since these regs include more stuff then PM, but let's
keep for legacy reasons.
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++--
drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++---------------
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ce19847273e..b083a841815e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -651,6 +651,8 @@ struct intel_irq {
/* protects the irq masks */
spinlock_t lock;
bool display_interrupts_enabled;
+ u32 pm_imr;
+ u32 pm_ier;
};
struct intel_rps {
@@ -1571,8 +1573,6 @@ struct drm_i915_private {
u32 de_irq_mask[I915_MAX_PIPES];
};
u32 gt_irq_mask;
- u32 pm_imr;
- u32 pm_ier;
u32 pm_rps_events;
u32 pm_guc_events;
u32 pipestat_irq_mask[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 754c44569cc4..13c76571da09 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -400,7 +400,7 @@ static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
static void write_pm_imr(struct drm_i915_private *dev_priv)
{
i915_reg_t reg;
- u32 mask = dev_priv->pm_imr;
+ u32 mask = dev_priv->irq.pm_imr;
if (INTEL_GEN(dev_priv) >= 11) {
reg = GEN11_GPM_WGBOXPERF_INTR_MASK;
@@ -419,7 +419,7 @@ static void write_pm_imr(struct drm_i915_private *dev_priv)
static void write_pm_ier(struct drm_i915_private *dev_priv)
{
i915_reg_t reg;
- u32 mask = dev_priv->pm_ier;
+ u32 mask = dev_priv->irq.pm_ier;
if (INTEL_GEN(dev_priv) >= 11) {
reg = GEN11_GPM_WGBOXPERF_INTR_ENABLE;
@@ -450,12 +450,12 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
lockdep_assert_held(&dev_priv->irq.lock);
- new_val = dev_priv->pm_imr;
+ new_val = dev_priv->irq.pm_imr;
new_val &= ~interrupt_mask;
new_val |= (~enabled_irq_mask & interrupt_mask);
- if (new_val != dev_priv->pm_imr) {
- dev_priv->pm_imr = new_val;
+ if (new_val != dev_priv->irq.pm_imr) {
+ dev_priv->irq.pm_imr = new_val;
write_pm_imr(dev_priv);
}
}
@@ -496,7 +496,7 @@ static void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, u32 enable_mas
{
lockdep_assert_held(&dev_priv->irq.lock);
- dev_priv->pm_ier |= enable_mask;
+ dev_priv->irq.pm_ier |= enable_mask;
write_pm_ier(dev_priv);
gen6_unmask_pm_irq(dev_priv, enable_mask);
/* unmask_pm_irq provides an implicit barrier (POSTING_READ) */
@@ -506,7 +506,7 @@ static void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, u32 disable_m
{
lockdep_assert_held(&dev_priv->irq.lock);
- dev_priv->pm_ier &= ~disable_mask;
+ dev_priv->irq.pm_ier &= ~disable_mask;
__gen6_mask_pm_irq(dev_priv, disable_mask);
write_pm_ier(dev_priv);
/* though a barrier is missing here, but don't really need a one */
@@ -3941,11 +3941,11 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev)
*/
if (HAS_ENGINE(dev_priv, VECS0)) {
pm_irqs |= PM_VEBOX_USER_INTERRUPT;
- dev_priv->pm_ier |= PM_VEBOX_USER_INTERRUPT;
+ dev_priv->irq.pm_ier |= PM_VEBOX_USER_INTERRUPT;
}
- dev_priv->pm_imr = 0xffffffff;
- GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->pm_imr, pm_irqs);
+ dev_priv->irq.pm_imr = 0xffffffff;
+ GEN3_IRQ_INIT(uncore, GEN6_PM, dev_priv->irq.pm_imr, pm_irqs);
}
}
@@ -4071,15 +4071,16 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)
};
- dev_priv->pm_ier = 0x0;
- dev_priv->pm_imr = ~dev_priv->pm_ier;
+ dev_priv->irq.pm_ier = 0x0;
+ dev_priv->irq.pm_imr = ~dev_priv->irq.pm_ier;
GEN8_IRQ_INIT_NDX(uncore, GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
GEN8_IRQ_INIT_NDX(uncore, GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
/*
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled. Same wil be the case for GuC interrupts.
*/
- GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->pm_imr, dev_priv->pm_ier);
+ GEN8_IRQ_INIT_NDX(uncore, GT, 2, dev_priv->irq.pm_imr,
+ dev_priv->irq.pm_ier);
GEN8_IRQ_INIT_NDX(uncore, GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
}
@@ -4192,8 +4193,8 @@ static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
* RPS interrupts will get enabled/disabled on demand when RPS itself
* is enabled/disabled.
*/
- dev_priv->pm_ier = 0x0;
- dev_priv->pm_imr = ~dev_priv->pm_ier;
+ dev_priv->irq.pm_ier = 0x0;
+ dev_priv->irq.pm_imr = ~dev_priv->irq.pm_ier;
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_ENABLE, 0);
I915_WRITE(GEN11_GPM_WGBOXPERF_INTR_MASK, ~0);
}
--
2.20.1
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