Quoting Mika Kuoppala (2019-04-10 11:59:22) > With gen11 the interrupt registers are shared between 2 engines, > with Engine1 instance being upper word and Engine0 instance being > lower. Annoyingly gen11 selected the pm interrupts to be in the > Engine1 instance. > > Rectify the situation by shifting the access accordingly, > based on gen. > > v2: comments, warn on overzealous rps_events > > Bugzilla: https://bugzilla.freedesktop.org/show_bug.cgi?id=108059 > Testcase: igt/i915_pm_rps@min-max-config-loaded > Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> > Signed-off-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
