== Series Details == Series: series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment (rev2) URL : https://patchwork.freedesktop.org/series/58974/ State : warning == Summary == $ dim checkpatch origin/drm-tip 73fa7ed439e6 drm/i915/psr: Update PSR2 SU corruption workaround comment 0ca6002ada07 drm/i915: Remove unused VLV/CHV PSR registers 5ce75180483f drm/i915/psr: Initialize PSR mutex even when sink is not reliable e47e5b39db34 drm/i915/psr: Do not enable PSR in interlaced mode for all GENs 9f93f7096863 drm/i915/bdw+: Move misc display IRQ handling to it own function 43add19f1fa5 drm/i915/psr: Remove partial PSR support on multiple transcoders a46b5a8681d1 drm/i915: Make PSR registers relative to transcoders -:93: WARNING:LONG_LINE: line over 100 characters #93: FILE: drivers/gpu/drm/i915/i915_reg.h:254: + INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \ -:109: WARNING:LONG_LINE: line over 100 characters #109: FILE: drivers/gpu/drm/i915/i915_reg.h:4217: +#define _TRANS2_PSR(reg) (_TRANS2(dev_priv->psr.transcoder, (reg)) - dev_priv->psr.mmio_base_adjust) -:135: WARNING:LONG_LINE_COMMENT: line over 100 characters #135: FILE: drivers/gpu/drm/i915/i915_reg.h:4266: +#define EDP_PSR_AUX_DATA(i) _MMIO(_TRANS2_PSR(_SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */ total: 0 errors, 3 warnings, 0 checks, 166 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
