Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> writes: > Quoting Daniele Ceraolo Spurio (2019-01-23 02:32:27) >> When reading GEN11_GT_INTR_DWx closely after enabling the interrupts >> in gen11_irq_postinstall, the returned value is garbage. This can >> cause other parts of the setup code (e.g. gen11_reset_one_iir) to >> think that there are interrupts to be cleared when there are none. >> >> The garbage value is only seen on the first read done after the enable, >> so this looks like a posting issue. Adding a posting read after enabling >> the interrupts does indeed fix the problem. >> >> Note that the posting read has been purposely added outside of >> gen11_master_intr_enable since the issue has only been observed when the >> full interrupt setup is performed. >> >> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx> > > irq regs and flushing stale results (side effect or double buffering? or > maybe latching?), seem to go hand in hand. > > Acked-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Pushed. Thank you for patch and ack. -Mika _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
