On 07/01/2019 12:54, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-01-07 12:50:24)
On 05/01/2019 02:40, Carlos Santa wrote:
+static void gen8_emit_breadcrumb_vcs(struct i915_request *request, u32 *cs)
+{
+ /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
+ BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
+
+ cs = gen8_emit_ggtt_write(cs, request->global_seqno,
+ intel_hws_seqno_address(request->engine));
+ *cs++ = MI_USER_INTERRUPT;
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+
+ // stop_watchdog at the very end of the ring commands
+ if (request->gem_context->__engine[VCS].watchdog_threshold != 0)
VCS is wrong. Whole check needs to be to_intel_context(ctx,
engine)->watchdog_threshold I think.
You too! rq->hw_context->watchdog_threshold. It's as if hw_context may
not even be part of gem_context...
Oops.. this is what happens when you just review and review - new stuff
does not get ingrained in memory unless typing it enough. :)
Regards,
Tvrtko
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