On Tue, Nov 27, 2018 at 07:32:59PM +0530, Ramalingam C wrote: > At enable/disable of the HDCP encryption, for encryption status change > we need minimum one frame duration. And we might program this bit any > point(start/End) in the previous frame. > > With 20mSec, observed the timeout for change in encryption status. > Since this is not time critical operation and we need to hold on > until the status is changed, fixing the timeout to 50mSec. (Based on > trial and error method!) > > Signed-off-by: Ramalingam C <ramalingam.c@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_hdcp.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c > index bd60d0e7bbfa..156b14d19e09 100644 > --- a/drivers/gpu/drm/i915/intel_hdcp.c > +++ b/drivers/gpu/drm/i915/intel_hdcp.c > @@ -15,6 +15,7 @@ > #include "i915_reg.h" > > #define KEY_LOAD_TRIES 5 > +#define TIME_FOR_ENCRYPT_STATUS_CHANGE 50 ENCRYPT_STATUS_CHANGE_TIMEOUT_MS please with that fixed, Reviewed-by: Sean Paul <sean@xxxxxxxxxx> > > static > bool intel_hdcp_is_ksv_valid(u8 *ksv) > @@ -638,7 +639,8 @@ static int intel_hdcp_auth(struct intel_digital_port *intel_dig_port, > > /* Wait for encryption confirmation */ > if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), > - HDCP_STATUS_ENC, HDCP_STATUS_ENC, 20)) { > + HDCP_STATUS_ENC, HDCP_STATUS_ENC, > + TIME_FOR_ENCRYPT_STATUS_CHANGE)) { > DRM_ERROR("Timed out waiting for encryption\n"); > return -ETIMEDOUT; > } > @@ -668,7 +670,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector) > > I915_WRITE(PORT_HDCP_CONF(port), 0); > if (intel_wait_for_register(dev_priv, PORT_HDCP_STATUS(port), ~0, 0, > - 20)) { > + TIME_FOR_ENCRYPT_STATUS_CHANGE)) { > DRM_ERROR("Failed to disable HDCP, timeout clearing status\n"); > return -ETIMEDOUT; > } > -- > 2.7.4 > > _______________________________________________ > dri-devel mailing list > dri-devel@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/dri-devel -- Sean Paul, Software Engineer, Google / Chromium OS _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx