Vandita, As we discussed earlier, we need to select clock for PORT_B as well in dual link video scenario even though we are going to use same DPLL for both the Ports. This will be done by DPCLKA_CFGCR0_DDI_CLK_SEL. icl_map_plls_to_ports inside haswell_crtc_enable() doesn't take care of that as its DSI specific requirement. Regards, Madhav > -----Original Message----- > From: Kulkarni, Vandita > Sent: Tuesday, November 27, 2018 3:09 PM > To: intel-gfx@xxxxxxxxxxxxxxxxxxxxx > Cc: Chauhan, Madhav <madhav.chauhan@xxxxxxxxx>; Nikula, Jani > <jani.nikula@xxxxxxxxx>; Syrjala, Ville <ville.syrjala@xxxxxxxxx>; Kulkarni, > Vandita <vandita.kulkarni@xxxxxxxxx> > Subject: [PATCH 0/6] ICL DSI PLL enable > > ICL DSI uses DPLL. > As per the discussion with hw team, the same sequence can be used for > enabling DPLL for mipi dsi as well. Hence reusing the dpll functions from icl > pll manager. > In addition to that we need to program > the esc clock register before enabling dsi. > > This has been tested on git://people.freedesktop.org/~jani/drm > and the patches are rebased on this. > > Madhav Chauhan (3): > drm/i915/icl: Calculate DPLL params for DSI > drm/i915/icl: Gate clocks for DSI > drm/i915/icl: Ungate DSI clocks > > Vandita Kulkarni (3): > drm/i915/icl: Use the same pll functions for dsi > drm/i915/icl: Get port clock from pll. > drm/i915/icl: Update port clock in compute config > > drivers/gpu/drm/i915/icl_dsi.c | 62 > ++++++++++++++++++++++++++++++++--- > drivers/gpu/drm/i915/intel_ddi.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 4 ++- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 ++-- > drivers/gpu/drm/i915/intel_dsi.h | 4 +++ > 5 files changed, 68 insertions(+), 10 deletions(-) > > -- > 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
