On Fri, Nov 09, 2018 at 04:58:20PM +0200, Imre Deak wrote:
> A DMC bug on GEN9 big core machines fails to restore the driver's
> request bits for the PW1 and MISC_IO power wells after a DC5/6
> entry->exit sequence. As a consequence the driver's subsequent check for
> the enabled status of these power wells will fail, as the check
> considers the power wells being enabled only if both the status and
> request bits are set. To work around this borrow the request bits from
> BIOS's own request register in which DMC forces on the request bits when
> exiting from DC5/6.
>
> This fixes a problem reported by Ramalingam, where HDCP init failed,
> since PW1 reported itself as being disabled, while in reality it was
> enabled.
>
> Reported-by: Ramalingam C <ramalingam.c@xxxxxxxxx>
> Cc: Ramalingam C <ramalingam.c@xxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index f945db6ea420..9c49b876055d 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -493,11 +493,25 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> const struct i915_power_well_regs *regs = power_well->desc->hsw.regs;
> + enum i915_power_well_id id = power_well->desc->id;
> int pw_idx = power_well->desc->hsw.idx;
> u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
> HSW_PWR_WELL_CTL_STATE(pw_idx);
> + u32 val;
> +
> + val = I915_READ(regs->driver);
> +
> + /*
> + * On GEN9 big core due to a DMC bug the driver's request bits for PW1
> + * and the MISC_IO PW will be not restored, so check instead for the
> + * BIOS's own request bits, which are forced-on for these power wells
> + * when exiting DC5/6.
> + */
> + if (IS_GEN9(dev_priv) && !IS_GEN9_LP(dev_priv) &&
IS_GEN9_BC() ?
Apart from that
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> + (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
> + val |= I915_READ(regs->bios);
>
> - return (I915_READ(regs->driver) & mask) == mask;
> + return (val & mask) == mask;
> }
>
> static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> --
> 2.13.2
--
Ville Syrjälä
Intel
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