On Thu, Nov 01, 2018 at 05:05:58PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > > The plane color correction registers are single buffered. So > ideally we would write them at the start of vblank just after the > double buffered plane registers have been latched. Since we have > no convenient way to do that for now let's at least move the > single buffered register writes to happen after the double > buffered registers have been written. Should we move this all the way out of the vblank evasion? I realize that vlv is only two registers total so it's not a big deal, but I know Uma is working on the plane color management stuff for later platforms where we have a bunch of registers to write, so maybe we should setup the callsite now? On a similar note, I notice our single-buffered pipe-level color management registers are written before evasion right now...should we move that to after the evasion as well? Matt > > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_sprite.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index 455b2d0cbaa6..84c5f532fba5 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -718,8 +718,6 @@ vlv_update_plane(struct intel_plane *plane, > > spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); > > - vlv_update_clrc(plane_state); > - > I915_WRITE_FW(SPSTRIDE(pipe, plane_id), > plane_state->color_plane[0].stride); > I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x); > @@ -747,6 +745,8 @@ vlv_update_plane(struct intel_plane *plane, > I915_WRITE_FW(SPSURF(pipe, plane_id), > intel_plane_ggtt_offset(plane_state) + sprsurf_offset); > > + vlv_update_clrc(plane_state); > + > spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); > } > > -- > 2.18.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Matt Roper Graphics Software Engineer IoTG Platform Enabling & Development Intel Corporation (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
