From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
First a bunch of cleanups and reordering of the plane register
update sequence to make it potentially more atomic, then we
move the SKL+ plane wm/ddb programming into the plane
update/disable hooks, and finally we change the order in which
the planes gets updated to avoid accidental ddb overlaps in
case a vblank sneaks in while we're reprogramming the planes
(as that could even cause a system hang). There are a few
updates to the watermark code as well that started to bug me
while doing this.
Entire thing available here:
git://github.com/vsyrjala/linux.git skl_plane_ddb_wm_update
Ville Syrjälä (14):
drm/i915: Nuke posting reads from plane update/disable funcs
drm/i915: Clean up skl_program_scaler()
drm/i915: Remove the PS_PWR_GATE write from skl_program_scaler()
drm/i915: Polish the skl+ plane keyval/msk/max register setup
drm/i915: Clean up skl+ PLANE_POS vs. scaler handling
drm/i915: Reorganize plane register writes to make them more atomic
drm/i915: Move single buffered plane register writes to the end
drm/i915: Generalize skl_ddb_allocation_overlaps()
drm/i915: Introduce crtc_state->update_planes bitmask
drm/i915: Pass the new crtc_state to ->disable_plane()
drm/i915: Fix latency==0 handling for level 0 watermark on skl+
drm/i915: Remove some useless zeroing on skl+ wm calculations
drm/i915: Move ddb/wm programming into plane update/disable hooks on
skl+
drm/i915: Commit skl+ planes in an order that avoids ddb overlaps
drivers/gpu/drm/i915/i915_debugfs.c | 21 +-
drivers/gpu/drm/i915/i915_drv.h | 3 -
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_atomic.c | 1 +
drivers/gpu/drm/i915/intel_atomic_plane.c | 102 ++++-
drivers/gpu/drm/i915/intel_display.c | 125 +++---
drivers/gpu/drm/i915/intel_display.h | 19 +-
drivers/gpu/drm/i915/intel_drv.h | 29 +-
drivers/gpu/drm/i915/intel_pm.c | 483 ++++++++++------------
drivers/gpu/drm/i915/intel_sprite.c | 185 +++++----
10 files changed, 518 insertions(+), 452 deletions(-)
--
2.18.1
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