On Fri, Jun 22, 2012 at 06:53:01PM +0100, Chris Wilson wrote: > On Fri, 22 Jun 2012 10:40:22 -0700, Keith Packard <keithp at keithp.com> wrote: > > Chris Wilson <chris at chris-wilson.co.uk> writes: > > > > > On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard <keithp at keithp.com> wrote: > > > > > It was structured to minimise lane count because certain chipsets did > > > not wire up all the lanes, right? Is that still relevant as we are using > > > the advertised max_lane_count from the DPCD now? > > > > We've always used the max_lane_count from dpcd; has there been some > > recent change that fixed usage of that? What I recall is one acer laptop > > that advertised 4 lanes but had only wired up two of them. > > The only recentish change was your > > commit 9a10f401a401ca69c6537641c8fc0d6b57b5aee8 > Author: Keith Packard <keithp at keithp.com> > Date: Wed Nov 2 13:03:47 2011 -0700 > > drm/i915: Use DPCD value for max DP lanes. > > The BIOS VBT value for an eDP panel has been shown to be incorrect on > one machine, and we haven't found any machines where the DPCD value > was wrong, so we'll use the DPCD value everywhere. > > We can but hope that no manufacturer lies in the DPCD. Ok, I've merged this patch because it fixes a regression and this commit Chris has dug out seems to indicate that we won't hit any known issues on eDP panels. I guess if it blows up again, we'll have to take another look. -Daniel -- Daniel Vetter Mail: daniel at ffwll.ch Mobile: +41 (0)79 365 57 48
