Chris Wilson <chris at chris-wilson.co.uk> writes: > On Thu, 21 Jun 2012 18:13:19 -0700, Keith Packard <keithp at keithp.com> wrote: > It was structured to minimise lane count because certain chipsets did > not wire up all the lanes, right? Is that still relevant as we are using > the advertised max_lane_count from the DPCD now? We've always used the max_lane_count from dpcd; has there been some recent change that fixed usage of that? What I recall is one acer laptop that advertised 4 lanes but had only wired up two of them. -- keith.packard at intel.com -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 827 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20120622/7cd5a7d3/attachment.pgp>
