On Mon, Oct 15, 2018 at 02:50:35PM -0700, Anusha Srivatsa wrote:
> If the panel supports FEC, the driver has to
> set the FEC_READY bit in the dpcd register:
> FEC_CONFIGURATION.
>
> This has to happen before link training.
>
> v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
> - change commit message. (Gaurav)
>
> v3: rebased.
>
> Cc: Gaurav K Singh <gaurav.k.singh@xxxxxxxxx>
> Cc: Jani Nikula <jani.nikula@xxxxxxxxxxxxxxx>
> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
This looks good to me.
Reviewed-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
Manasi
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 17 +++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 3 +++
> 3 files changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 2db6284d3a96..f531900165bf 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2909,6 +2909,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
> intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> DP_DECOMPRESSION_EN);
> + intel_dp_sink_set_fec_ready(intel_dp, crtc_state, DP_FEC_READY);
> intel_dp_start_link_train(intel_dp);
> if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
> intel_dp_stop_link_train(intel_dp);
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 318494afd14a..b4e8af3142a2 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3000,6 +3000,23 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> state == DP_DECOMPRESSION_EN ? "enable" : "disable");
> }
>
> +void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + int state)
> +{
> + int ret;
> +
> + if (!crtc_state->dsc_params.compression_enable)
> + return;
> +
> + if (intel_dp_is_edp(intel_dp))
> + return;
> +
> + ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, state);
> + if (ret < 0)
> + DRM_DEBUG_KMS("Failed to get FEC enabled in sink\n");
> +}
> +
> /* If the sink supports it, try to set the power state appropriately */
> void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
> {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index b87ea052c9ca..fbc9fa06e8be 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1709,6 +1709,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
> void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state,
> int state);
> +void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + int state);
> void intel_dp_encoder_reset(struct drm_encoder *encoder);
> void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
> void intel_dp_encoder_destroy(struct drm_encoder *encoder);
> --
> 2.17.1
>
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