With Display Compression, the bit error in the pixel stream can turn into a significant corruption on the screen. The DP1.4 adds FEC - Forward Error Correction scheme which uses Reed-Solomon parity/correction check generated by the source and used by the sink to detect and correct small numbers of bit errors in the compressed stream. v2: Avoid doing aux channel read eberytime we check for FEC support. Instead cache the value of the DPCD registers, similar to the DSC implementaion (Jani) This is rebased on top of Manasi's End-to-end DSC Implementation: https://patchwork.freedesktop.org/series/47514/ Tested on Odelia Board after applying the FEC workaround. Anusha Srivatsa (6): i915/dp/fec: Cache the FEC_CAPABLE DPCD register i915/dp/fec: Check for FEC Support drm/dp/fec: DRM helper for Forward Error Correction drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION i915/dp/fec: Configure the Forward Error Correction bits. drm/i915/fec: Disable FEC state. drivers/gpu/drm/i915/i915_reg.h | 2 + drivers/gpu/drm/i915/intel_ddi.c | 5 ++ drivers/gpu/drm/i915/intel_dp.c | 82 +++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_drv.h | 9 +++- include/drm/drm_dp_helper.h | 7 +++ 5 files changed, 102 insertions(+), 3 deletions(-) -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
