== Series Details == Series: Display Stream Compression enabling on eDP/DP (rev5) URL : https://patchwork.freedesktop.org/series/47514/ State : failure == Summary == = CI Bug Log - changes from CI_DRM_4945 -> Patchwork_10385 = == Summary - FAILURE == Serious unknown changes coming with Patchwork_10385 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10385, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/47514/revisions/5/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10385: === IGT changes === ==== Possible regressions ==== igt@debugfs_test@read_all_entries: fi-icl-u: PASS -> FAIL ==== Warnings ==== igt@prime_vgem@basic-fence-flip: fi-ivb-3520m: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_10385 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_module_reload@basic-reload: fi-glk-j4005: NOTRUN -> DMESG-WARN (fdo#106248, fdo#106725) igt@gem_exec_suspend@basic-s3: fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718) igt@kms_flip@basic-flip-vs-modeset: fi-ilk-650: PASS -> DMESG-WARN (fdo#106387) igt@kms_frontbuffer_tracking@basic: fi-icl-u: SKIP -> FAIL (fdo#107766) igt@kms_pipe_crc_basic@read-crc-pipe-a: fi-icl-u: PASS -> FAIL (fdo#107766) +17 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: fi-bdw-samus: NOTRUN -> INCOMPLETE (fdo#107773) ==== Possible fixes ==== igt@gem_exec_suspend@basic-s3: fi-bdw-samus: INCOMPLETE (fdo#107773) -> PASS igt@kms_flip@basic-flip-vs-dpms: fi-hsw-4770r: DMESG-WARN (fdo#105602) -> PASS fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106387 https://bugs.freedesktop.org/show_bug.cgi?id=106387 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107766 https://bugs.freedesktop.org/show_bug.cgi?id=107766 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 == Participating hosts (44 -> 37) == Additional (1): fi-glk-j4005 Missing (8): fi-ilk-m540 fi-bxt-dsi fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-snb-2520m fi-ctg-p8600 fi-pnv-d510 == Build changes == * Linux: CI_DRM_4945 -> Patchwork_10385 CI_DRM_4945: d9b2bbbdba15cadca76ffd3ff0476e71222d671b @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4671: b121f7d42c260ae3a050c3f440d1c11f7cff7d1a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10385: aa4d5bb53d34ebfed0986819c902a347bb6c51d6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == aa4d5bb53d34 drm/i915/dsc: Force DSC enable if requested by IGT/userspace 95032188e13f drm/i915/dsc: Add Per connector debugfs node for DSC support/enable 4fd1d74f4b66 drm/i915/dsc: Enable and disable appropriate power wells for VDSC 1e8be3413e03 drm/i915/dp: Disable DSC in source by disabling DSS CTL bits 5dbf3482277d drm/i915/dp: Configure Display stream splitter registers during DSC enable 93f7f38daf9d drm/i915/icl: Add Display Stream Splitter control registers 8a405e9334df drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes bbf10b6974d7 drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs e6e4315ae809 drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling 1123bd490e53 drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI ea1eee8724a0 drm/i915/dp: Enable/Disable DSC in DP Sink 7c2422670f1d drm/i915/dsc: Compute Rate Control parameters for DSC a3b30949f4db drm/i915/dsc: Define & Compute VESA DSC params 3341aaf29568 drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants 2ac87eee4715 drm/i915/dp: Do not enable PSR2 if DSC is enabled e787d64e456e drm/i915/dp: Compute DSC pipe config in atomic check 44847e209caf drm/i915/dp: Add DSC params and DSC config to intel_crtc_state 3a01d6ad7d7a drm/dsc: Add helpers for DSC picture parameter set infoframes a5d4c8c5cbf2 drm/dsc: Define Rate Control values that do not change over configurations ed145dd80208 drm/dsc: Define VESA Display Stream Compression Capabilities cf5d8f25d9a3 drm/dsc: Define Display Stream Compression PPS infoframe 423a3126657c drm/dp: Define payload size for DP SDP PPS packet eb37babb198f drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported b7b131dde493 drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC bfdecf2dc03b drm/dp: DRM DP helper/macros to get DP sink DSC parameters 6d04d97a2398 drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init f58388d95d62 drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT f0a2fb715544 drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10385/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
