VESA has developed an industry standard Display Stream Compression(DSC) for interoperable, visually lossless compression over display links to address the needs for higher resolution displays. This patch series enables DSC on Gen 10 eDP and Gen 11 eDP/DP panels. This implementation is based on VESA DP 1.4 and DSC specifications. These patches have been validated on 1080p eDP 1.4 panel with DSC support and FPGA based DP 1.4 sink device for following configurations: - DSC with both VDSC engines enabled - DSC with only Left VDSC engine enabled - DSC for Input = 24bpp, Output = 8bpp - DSC for Input = 24bpp, Output = 10bpp - DSC for Input = 24bpp, output = 12bpp This patch series is a spin of some patches in the previous series: https://patchwork.freedesktop.org/series/47514/ based on review comments. Additionally this also adds some DSC support debugfs nodes for IGT tests. Corresponding IGT test sent to the igt-dev M-L. Anusha Srivatsa (1): drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Gaurav K Singh (4): drm/dsc: Define VESA Display Stream Compression Capabilities drm/i915/dsc: Define & Compute VESA DSC params drm/i915/dsc: Compute Rate Control parameters for DSC drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare (21): drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init drm/dp: DRM DP helper/macros to get DP sink DSC parameters drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported drm/dp: Define payload size for DP SDP PPS packet drm/dsc: Define Display Stream Compression PPS infoframe drm/dsc: Add helpers for DSC picture parameter set infoframes drm/i915/dp: Add DSC params and DSC config to intel_crtc_state drm/i915/dp: Compute DSC pipe config in atomic check drm/i915/dp: Do not enable PSR2 if DSC is enabled drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes drm/i915/dp: Configure Display stream splitter registers during DSC enable drm/i915/dp: Disable DSC in source by disabling DSS CTL bits drm/i915/dsc: Enable and disable appropriate power wells for VDSC drm/i915/dsc: Add Per connector debugfs node for DSC support/enable drm/i915/dsc: Force DSC enable if requested by IGT/userspace Srivatsa, Anusha (2): drm/dsc: Define Rate Control values that do not change over configurations drm/i915/icl: Add Display Stream Splitter control registers Documentation/gpu/drm-kms-helpers.rst | 12 + drivers/gpu/drm/Makefile | 2 +- drivers/gpu/drm/drm_dp_helper.c | 90 ++ drivers/gpu/drm/drm_dsc.c | 223 +++++ drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_debugfs.c | 83 +- drivers/gpu/drm/i915/i915_drv.h | 5 + drivers/gpu/drm/i915/i915_reg.h | 35 + drivers/gpu/drm/i915/intel_ddi.c | 5 + drivers/gpu/drm/i915/intel_display.c | 39 +- drivers/gpu/drm/i915/intel_display.h | 4 +- drivers/gpu/drm/i915/intel_dp.c | 361 +++++++- drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/intel_drv.h | 24 + drivers/gpu/drm/i915/intel_hdmi.c | 23 +- drivers/gpu/drm/i915/intel_psr.c | 16 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +- drivers/gpu/drm/i915/intel_vdsc.c | 1101 +++++++++++++++++++++++ include/drm/drm_dp_helper.h | 40 + include/drm/drm_dsc.h | 491 ++++++++++ 20 files changed, 2513 insertions(+), 50 deletions(-) create mode 100644 drivers/gpu/drm/drm_dsc.c create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c create mode 100644 include/drm/drm_dsc.h -- 2.18.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
