Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx> writes:
> Shader feature to prefetch binding tables does not support 16:6 18:8 BTP
> formats.
s/formats./,causing lower performance if used. And with fault
handling enabled can cause gpu hangs.
> Disabling demand prefetch would disable binding table prefetch.
>
Also please add:
References: HSDES#1406609255, HSDES#1406573985
And as mentioned earlied, this is fixed on C0 so limit
range to ICL_REVID_B0.
Thanks,
-Mika
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_workarounds.c | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4b472bc2d26d..117ae5bf647c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7411,6 +7411,9 @@ enum {
> #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c)
> #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11)
>
> +#define GEN7_SARCHKMD _MMIO(0xB000)
> +#define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31)
> +
> #define GEN7_L3SQCREG1 _MMIO(0xB010)
> #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
>
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 54a63c9b694f..9d5f48b98803 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -909,6 +909,12 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> /* WaEnable32PlaneMode:icl */
> I915_WRITE(GEN9_CSFE_CHICKEN1_RCS,
> _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE));
> +
> + /* Wa_1406609255:icl (pre-prod) */
> + if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
> + I915_WRITE(GEN7_SARCHKMD,
> + I915_READ(GEN7_SARCHKMD) |
> + GEN7_DISABLE_DEMAND_PREFETCH);
> }
>
> void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv)
> --
> 2.9.3
>
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