On BDW+ the linear source buffer of 2d source copy needs to start from
cache line boundary based on hardware design. Apply this alignment policy
to all platforms accordingly.
v2: Apply these changes only to SKL+ for not breaking old platforms
based on code review (Chris).
v3: Apply these changes for BDW+ onward chipsets based on hardware
design teams' inputs.
Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Signed-off-by: Guang Bai <guang.bai@xxxxxxxxx>
---
src/sna/sna_io.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/sna/sna_io.c b/src/sna/sna_io.c
index d32bd58..35b90e5 100644
--- a/src/sna/sna_io.c
+++ b/src/sna/sna_io.c
@@ -1077,12 +1077,16 @@ tile:
/* Count the total number of bytes to be read and allocate a
* single buffer large enough. Or if it is very small, combine
- * with other allocations. */
+ * with other allocations. Each sub-buffer starting point
+ * (offset) should be aligned to 64-byte cache line boundary
+ * for BDW+ according to hardware design specifications.
+ */
offset = 0;
for (n = 0; n < nbox_this_time; n++) {
int height = box[n].y2 - box[n].y1;
int width = box[n].x2 - box[n].x1;
offset += PITCH(width, dst->drawable.bitsPerPixel >> 3) * height;
+ offset = ALIGN(offset, 64);
}
src_bo = kgem_create_buffer(kgem, offset,
@@ -1143,6 +1147,7 @@ tile:
box++;
offset += pitch * height;
+ offset = ALIGN(offset, 64);
} while (--nbox_this_time);
assert(offset == __kgem_buffer_size(src_bo));
sigtrap_put();
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
