Instead of defining all registers twice, define just a PCH_GPIO_BASE
that has the same address as PCH_GPIO_A and use that to calculate all
the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
the same thing.
This also rewrites the GMBUS[05] registers since they depend on
gpio_mmio_base.
v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
macro to return a particular gpio address and move the enum out of
i915_reg.h (suggested by Jani)
Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
---
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 53 +++++++++++++++--------------
drivers/gpu/drm/i915/intel_drv.h | 16 +++++++++
drivers/gpu/drm/i915/intel_i2c.c | 16 ++++-----
4 files changed, 52 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index e39492aaff6c..e25a74fe753b 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2084,7 +2084,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
gmbus_mmio_write);
- MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(_MMIO(PCH_GPIO_BASE), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0424e45f88db..f8f71d577613 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3088,18 +3088,11 @@ enum i915_power_well_id {
/*
* GPIO regs
*/
-#define GPIOA _MMIO(0x5010)
-#define GPIOB _MMIO(0x5014)
-#define GPIOC _MMIO(0x5018)
-#define GPIOD _MMIO(0x501c)
-#define GPIOE _MMIO(0x5020)
-#define GPIOF _MMIO(0x5024)
-#define GPIOG _MMIO(0x5028)
-#define GPIOH _MMIO(0x502c)
-#define GPIOJ _MMIO(0x5034)
-#define GPIOK _MMIO(0x5038)
-#define GPIOL _MMIO(0x503C)
-#define GPIOM _MMIO(0x5040)
+#define GPIO_OFFSET 0x5010u
+#define PCH_GPIO_BASE (0xc0000u + GPIO_OFFSET)
+#define VLV_GPIO_BASE (VLV_DISPLAY_BASE + GPIO_OFFSET)
+#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 4 * (gpio))
+
# define GPIO_CLOCK_DIR_MASK (1 << 0)
# define GPIO_CLOCK_DIR_IN (0 << 1)
# define GPIO_CLOCK_DIR_OUT (1 << 1)
@@ -3115,7 +3108,11 @@ enum i915_power_well_id {
# define GPIO_DATA_VAL_IN (1 << 12)
# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
-#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base + 0x5100) /* clock/port select */
+#define GMBUS_OFFSET 0x5100u
+
+/* clock/port select */
+#define GMBUS0 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET)
#define GMBUS_AKSV_SELECT (1 << 11)
#define GMBUS_RATE_100KHZ (0 << 8)
#define GMBUS_RATE_50KHZ (1 << 8)
@@ -3141,7 +3138,10 @@ enum i915_power_well_id {
#define GMBUS_PIN_12_TC4_ICP 12
#define GMBUS_NUM_PINS 13 /* including 0 */
-#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base + 0x5104) /* command/status */
+
+/* command/status */
+#define GMBUS1 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0x4)
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
#define GMBUS_ENT (1 << 29) /* enable timeout */
@@ -3155,7 +3155,10 @@ enum i915_power_well_id {
#define GMBUS_SLAVE_ADDR_SHIFT 1
#define GMBUS_SLAVE_READ (1 << 0)
#define GMBUS_SLAVE_WRITE (0 << 0)
-#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base + 0x5108) /* status */
+
+/* status */
+#define GMBUS2 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0x8)
#define GMBUS_INUSE (1 << 15)
#define GMBUS_HW_WAIT_PHASE (1 << 14)
#define GMBUS_STALL_TIMEOUT (1 << 13)
@@ -3163,14 +3166,21 @@ enum i915_power_well_id {
#define GMBUS_HW_RDY (1 << 11)
#define GMBUS_SATOER (1 << 10)
#define GMBUS_ACTIVE (1 << 9)
-#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base + 0x510c) /* data buffer bytes 3-0 */
-#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base + 0x5110) /* interrupt mask (Pineview+) */
+
+/* data buffer bytes 3-0 */
+#define GMBUS3 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0xc)
+/* interrupt mask (Pineview+) */
+#define GMBUS4 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0x10)
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
#define GMBUS_NAK_EN (1 << 3)
#define GMBUS_IDLE_EN (1 << 2)
#define GMBUS_HW_WAIT_EN (1 << 1)
#define GMBUS_HW_RDY_EN (1 << 0)
-#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base + 0x5120) /* byte index */
+/* byte index */
+#define GMBUS5 _MMIO(dev_priv->gpio_mmio_base - GPIO_OFFSET \
+ + GMBUS_OFFSET + 0x20)
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
/*
@@ -7668,13 +7678,6 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define PCH_GPIOA _MMIO(0xc5010)
-#define PCH_GPIOB _MMIO(0xc5014)
-#define PCH_GPIOC _MMIO(0xc5018)
-#define PCH_GPIOD _MMIO(0xc501c)
-#define PCH_GPIOE _MMIO(0xc5020)
-#define PCH_GPIOF _MMIO(0xc5024)
-
#define PCH_GMBUS0 _MMIO(0xc5100)
#define PCH_GMBUS1 _MMIO(0xc5104)
#define PCH_GMBUS2 _MMIO(0xc5108)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 61e715ddd0d5..dedf87c58a95 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -152,6 +152,22 @@
* Display related stuff
*/
+enum i915_gpio {
+ GPIOA = 0,
+ GPIOB,
+ GPIOC,
+ GPIOD,
+ GPIOE,
+ GPIOF,
+ GPIOG,
+ GPIOH,
+ __GPIOI_UNUSED,
+ GPIOJ,
+ GPIOK,
+ GPIOL,
+ GPIOM,
+};
+
/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 97606c1be70d..f1c0b974daa6 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -37,7 +37,7 @@
struct gmbus_pin {
const char *name;
- i915_reg_t reg;
+ enum i915_gpio gpio;
};
/* Map gmbus pin pairs to names and registers. */
@@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
else
size = ARRAY_SIZE(gmbus_pins);
- return pin < size &&
- i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
+ return pin < size && get_gmbus_pin(dev_priv, pin)->name;
}
/* Intel GPIO access functions */
@@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
algo = &bus->bit_algo;
- bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
- i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
+ bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
bus->adapter.algo_data = algo;
algo->setsda = set_data;
algo->setscl = set_clock;
@@ -775,11 +773,11 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
return 0;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
+ dev_priv->gpio_mmio_base = VLV_GPIO_BASE;
else if (!HAS_GMCH_DISPLAY(dev_priv))
- dev_priv->gpio_mmio_base =
- i915_mmio_reg_offset(PCH_GPIOA) -
- i915_mmio_reg_offset(GPIOA);
+ dev_priv->gpio_mmio_base = PCH_GPIO_BASE;
+ else
+ dev_priv->gpio_mmio_base = GPIO_OFFSET;
mutex_init(&dev_priv->gmbus_mutex);
init_waitqueue_head(&dev_priv->gmbus_wait_queue);
--
2.17.1
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