On Fri, Jul 06, 2018 at 12:54:02PM +0100, Chris Wilson wrote: > If we have just completed a WC write, we must ensure that the WCB (Write > Combining Buffer) is flushed out to main memory before we can expect to > see the results. This is especially important when mixing WC with GTT as > the physical paths are different and cachelines are not naturally flushed. > > Testcase: igt/drv_selftests/live_coherency #gdg > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_gem.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 0c0a1a959d0b..be63e8bbb6d2 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -837,6 +837,10 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) > } > break; > > + case I915_GEM_DOMAIN_WC: > + wmb(); > + break; > + > case I915_GEM_DOMAIN_CPU: > i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); > break; > -- > 2.18.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
