On Wed, 2018-06-27 at 13:02 -0700, Tarun Vyas wrote:
> The PIPEDSL freezes on PSR entry and if PSR hasn't fully exited, then
> the pipe_update_start call schedules itself out to check back later.
>
> On ChromeOS-4.4 kernel, which is fairly up-to-date w.r.t drm/i915 but
> lags w.r.t core kernel code, hot plugging an external display
> triggers
> tons of "potential atomic update errors" in the dmesg, on *pipe A*. A
> closer analysis reveals that we try to read the scanline 3 times and
> eventually timeout, b/c PSR hasn't exited fully leading to a PIPEDSL
> stuck @ 1599. This issue is not seen on upstream kernels, b/c for
> *some*
> reason we loop inside intel_pipe_update start for ~2+ msec which in
> this
> case is more than enough to exit PSR fully, hence an *unstuck*
> PIPEDSL
> counter, hence no error. On the other hand, the ChromeOS kernel
> spends
> ~1.1 msec looping inside intel_pipe_update_start and hence errors out
> b/c the source is still in PSR.
>
> Regardless, we should wait for PSR exit (if PSR is disabled, we incur
> a ~1-2 usec penalty) before reading the PIPEDSL, b/c if we haven't
> fully exited PSR, then checking for vblank evasion isn't actually
> applicable.
>
> v4: Comment explaining psr_wait after enabling VBL interrupts (DK)
>
> v5: CAN_PSR() to handle platforms that don't support PSR.
>
> v6: Handle local_irq_disable on early return (Chris)
Series Reviewed-by: Dhinakaran Pandiyan
<dhinakaran.pandiyan@xxxxxxxxx>
Daniel's questions were addressed over IRC, I'll push this version if
they aren't any other concerns.
-DK
>
> Signed-off-by: Tarun Vyas <tarun.vyas@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_sprite.c | 20 ++++++++++++++++----
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 344c0e709b19..4990d6e84ddf 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -107,13 +107,21 @@ void intel_pipe_update_start(const struct
> intel_crtc_state *new_crtc_state)
> VBLANK_EVASION
> _TIME_US);
> max = vblank_start - 1;
>
> - local_irq_disable();
> -
> if (min <= 0 || max <= 0)
> - return;
> + goto irq_disable;
>
> if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
> - return;
> + goto irq_disable;
> +
> + /*
> + * Wait for psr to idle out after enabling the VBL
> interrupts
> + * VBL interrupts will start the PSR exit and prevent a PSR
> + * re-entry as well.
> + */
> + if (CAN_PSR(dev_priv) && intel_psr_wait_for_idle(dev_priv))
> + DRM_ERROR("PSR idle timed out, atomic update may
> fail\n");
> +
> + local_irq_disable();
>
> crtc->debug.min_vbl = min;
> crtc->debug.max_vbl = max;
> @@ -171,6 +179,10 @@ void intel_pipe_update_start(const struct
> intel_crtc_state *new_crtc_state)
> crtc->debug.start_vbl_count =
> intel_crtc_get_vblank_counter(crtc);
>
> trace_i915_pipe_update_vblank_evaded(crtc);
> + return;
> +
> +irq_disable:
> + local_irq_disable();
> }
>
> /**
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