On Thu, May 31, 2018 at 08:55:23AM +0300, Jani Nikula wrote:
> HAS_PCH_NOP() implies a PCH platform without south display, not generic
> disabled display. Prefer num_pipes == 0 for PCH independent checks.
>
> Cc: Ville Syrjala <ville.syrjala@xxxxxxxxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
>
> ---
>
> I'm actually not sure about this. What should VLV, CHV, BXT and GLK do
> in this branch if display gets disabled? See next patch.
> ---
> drivers/gpu/drm/i915/i915_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 530d6d0109b4..d6be1a08848d 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -5137,7 +5137,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ?
> LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
>
> - if (HAS_PCH_NOP(dev_priv)) {
> + if (INTEL_INFO(dev_priv)->num_pipes == 0) {
So we're specifically trying to disable the PCH display reset handshake.
That would only seem applicaple for platforms with a PCH. So PCH_NOP
seems like the correct thing to check here.
However since we're just clearing the bits I think it should actually
be safe to do this on non-PCH platforms as well. But with the current
code I think we'd end up poking at the wrong register on VLV. It should
probably use the IVB register instead of the HSW+ register.
> if (IS_IVYBRIDGE(dev_priv)) {
> u32 temp = I915_READ(GEN7_MSG_CTL);
> temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> --
> 2.11.0
--
Ville Syrjälä
Intel
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