On Tue, Jan 30, 2018 at 04:05:20PM +0100, Maarten Lankhorst wrote:
> According to bspec, result_lines > 31 is only a maximum for latency
> level 1 through 7.
>
> For level 0 the number of lines is ignored, so always write 0 there
> to prevent overflowing the 5 bits value.
>
> This is required to make NV12 work.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 26132fa6ebce..ed0ec0188962 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4805,6 +4805,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> res_blocks = result_prev->plane_res_b;
> }
>
> + /* The number of lines are ignored for the level 0 watermark. */
> + if (!level)
> + res_lines = 0;
> +
Looks like we could just skip computing res_lines entirely.
But this should work too so
Reviewed-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>a
> if (res_blocks >= ddb_allocation || res_lines > 31) {
> result->plane_en = false;
>
> --
> 2.15.1
--
Ville Syrjälä
Intel OTC
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