On Tue, Jan 30, 2018 at 02:54:11PM +0100, Maarten Lankhorst wrote:
> According to bspec, result_lines > 31 is only a maximum for latency
> level 1 through 7, so correctly apply the check there.
The register still has only 5 bits for the line watermark. However the
spec says "Hardware ignores the lines for the level 0 watermark.", so
I think what we should be doing is just setting the line watermark to
zero for level 0.
>
> This is required to make NV12 work.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 26132fa6ebce..f19a3fc2466e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4805,7 +4805,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
> res_blocks = result_prev->plane_res_b;
> }
>
> - if (res_blocks >= ddb_allocation || res_lines > 31) {
> + if (res_blocks >= ddb_allocation || (level >= 1 && level <= 7 && res_lines > 31)) {
> result->plane_en = false;
>
> /*
> --
> 2.15.1
>
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--
Ville Syrjälä
Intel OTC
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