On Fri, Dec 22, 2017 at 09:22:24PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Let's document why we claim hsub==8,vsub==16 for CCS even though the
> memory layout would suggest that we use 16x8 instead.
>
> Cc: Daniel Vetter <daniel@xxxxxxxx>
> Cc: Ben Widawsky <ben@xxxxxxxxxxxx>
> Cc: Jason Ekstrand <jason@xxxxxxxxxxxxxx>
> Cc: Daniel Stone <daniels@xxxxxxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Imo this needs an ack from Jason (or someone else who groks the CCS
layout), passsing on this one.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0cd355978ab4..83aec68537b4 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2387,6 +2387,13 @@ static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
> }
> }
>
> +/*
> + * 1 byte of CCS actually corresponds to 16x8 pixels on the main
> + * surface, and the memory layout for the CCS tile is 64x64 bytes.
> + * But since we're pretending the CCS tile is 128 bytes wide we
> + * adjust hsub/vsub here accordingly to 8x16 so that the
> + * bytes<->x/y conversions come out correct.
> + */
> static const struct drm_format_info ccs_formats[] = {
> { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, },
> --
> 2.13.6
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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