Hi 2012/1/26 Daniel Vetter <daniel.vetter at ffwll.ch>: > Hi all, > > http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced > I just tested your patch set and it didn't work: my monitor reported 1920x539 at 50Hz. We're missing something from patch "fixup interlace vertical timings confusion". The reg dump is attached. By the way, VTOTAL_B was 1078. We need to remove those "-1" and also those "-2". Look at ironlake_crtc_mode_set: we already do the subtractions when we write to HSYNC, HTOTAL, etc. From the register descriptions, those -1 are independent of interlaced or non-interlaced. I believe there was some confusion with these registers because intel_reg_dumper already re-adds +1 when showing the register values. Btw, git clone on fd.o is slow today :( -- Paulo Zanoni -------------- next part -------------- PGETBL_CTL: 0x00000000 GEN6_INSTDONE_1: 0xfffffffe GEN6_INSTDONE_2: 0xffffffff CPU_VGACNTRL: 0x80000000 (disabled) DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000 RR_HW_CTL: 0x00000000 (low 0, high 0) FDI_PLL_BIOS_0: 0xffffffff FDI_PLL_BIOS_1: 0xffffffff FDI_PLL_BIOS_2: 0xffffffff DISPLAY_PORT_PLL_BIOS_0: 0xffffffff DISPLAY_PORT_PLL_BIOS_1: 0xffffffff DISPLAY_PORT_PLL_BIOS_2: 0xffffffff FDI_PLL_FREQ_CTL: 0xffffffff PIPEACONF: 0xc0000050 (enabled, rotate 0, active, 6bpc) HTOTAL_A: 0x062d0555 (1366 active, 1582 total) HBLANK_A: 0x062d0555 (1366 start, 1582 end) HSYNC_A: 0x05c50585 (1414 start, 1478 end) VTOTAL_A: 0x031702ff (768 active, 792 total) VBLANK_A: 0x031702ff (768 start, 792 end) VSYNC_A: 0x030a0303 (772 start, 779 end) VSYNCSHIFT_A: 0x00000000 PIPEASRC: 0x055502ff (1366, 768) PIPEA_DATA_M1: 0x7e14a780 (TU 64, val 0x14a780 1353600) PIPEA_DATA_N1: 0x0020f580 (val 0x20f580 2160000) PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEA_DATA_N2: 0x00000000 (val 0x0 0) PIPEA_LINK_M1: 0x000125c0 (val 0x125c0 75200) PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000) PIPEA_LINK_M2: 0x00000000 (val 0x0 0) PIPEA_LINK_N2: 0x00000000 (val 0x0 0) DSPACNTR: 0xd8004400 (enabled) DSPABASE: 0x00000000 DSPASTRIDE: 0x00003400 (208) DSPASURF: 0x059d6000 DSPATILEOFF: 0x00000000 (0, 0) PIPEBCONF: 0xc0600000 (enabled, rotate 0, active, 8bpc) HTOTAL_B: 0x0a4f077f (1920 active, 2640 total) HBLANK_B: 0x0a4f077f (1920 start, 2640 end) HSYNC_B: 0x09bb098f (2448 start, 2492 end) VTOTAL_B: 0x04620435 (1078 active, 1123 total) VBLANK_B: 0x04620435 (1078 start, 1123 end) VSYNC_B: 0x04430439 (1082 start, 1092 end) VSYNCSHIFT_B: 0x00000000 DSPBCNTR: 0xd8004400 (enabled) DSPBBASE: 0x00001558 DSPBSTRIDE: 0x00003400 (208) DSPBSURF: 0x059d6000 DSPBTILEOFF: 0x00000556 (1366, 0) PIPEBSRC: 0x077f0437 (1920, 1080) PIPEB_DATA_M1: 0x7e1b30f0 (TU 64, val 0x1b30f0 1782000) PIPEB_DATA_N1: 0x0020f580 (val 0x20f580 2160000) PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0) PIPEB_DATA_N2: 0x00000000 (val 0x0 0) PIPEB_LINK_M1: 0x0001220a (val 0x1220a 74250) PIPEB_LINK_N1: 0x00041eb0 (val 0x41eb0 270000) PIPEB_LINK_M2: 0x00000000 (val 0x0 0) PIPEB_LINK_N2: 0x00000000 (val 0x0 0) PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFA_CTL_2: 0x00007e80 (vscale 0.988281) PFA_CTL_3: 0x00003f40 (vscale initial phase 0.494141) PFA_CTL_4: 0x00007d54 (hscale 0.979126) PFA_WIN_POS: 0x00000000 (0, 0) PFA_WIN_SIZE: 0x00000000 (0, 0) PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1) PFB_CTL_2: 0x00007ef2 (vscale 0.991760) PFB_CTL_3: 0x00003f79 (vscale initial phase 0.495880) PFB_CTL_4: 0x00007c40 (hscale 0.970703) PFB_WIN_POS: 0x00000000 (0, 0) PFB_WIN_SIZE: 0x00000000 (0, 0) PCH_DREF_CONTROL: 0x00001400 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable) PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125) PCH_DPLL_TMR_CFG: 0x0271186a PCH_SSC4_PARMS: 0x01204860 PCH_SSC4_AUX_PARMS: 0x000029c5 PCH_DPLL_SEL: 0x00000098 (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125) PCH_DPLL_ANALOG_CTL: 0x00008000 PCH_DPLL_A: 0x88040004 (enable, sdvo high speed no, mode LVDS, p2 Div 14, FPA0 P1 3, FPA1 P1 3, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_DPLL_B: 0xc4080008 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 4, FPA1 P1 4, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_FPA0: 0x00010c07 (n = 1, m1 = 12, m2 = 7) PCH_FPA1: 0x00010c07 (n = 1, m1 = 12, m2 = 7) PCH_FPB0: 0x00021007 (n = 2, m1 = 16, m2 = 7) PCH_FPB1: 0x00021007 (n = 2, m1 = 16, m2 = 7) TRANS_HTOTAL_A: 0x062d0555 (1366 active, 1582 total) TRANS_HBLANK_A: 0x062d0555 (1366 start, 1582 end) TRANS_HSYNC_A: 0x05c50585 (1414 start, 1478 end) TRANS_VTOTAL_A: 0x031702ff (768 active, 792 total) TRANS_VBLANK_A: 0x031702ff (768 start, 792 end) TRANS_VSYNC_A: 0x030a0303 (772 start, 779 end) TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0) TRANSA_DATA_N1: 0x00000000 (val 0x0 0) TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0) TRANSA_DATA_N2: 0x00000000 (val 0x0 0) TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0) TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0) TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0) TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0) TRANS_HTOTAL_B: 0x0a4f077f (1920 active, 2640 total) TRANS_HBLANK_B: 0x0a4f077f (1920 start, 2640 end) TRANS_HSYNC_B: 0x09bb098f (2448 start, 2492 end) TRANS_VTOTAL_B: 0x04620435 (1078 active, 1123 total) TRANS_VBLANK_B: 0x04620435 (1078 start, 1123 end) TRANS_VSYNC_B: 0x04430439 (1082 start, 1092 end) TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0) TRANSB_DATA_N1: 0x00000000 (val 0x0 0) TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0) TRANSB_DATA_N2: 0x00000000 (val 0x0 0) TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0) TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0) TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0) TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0) TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total) TRANS_HBLANK_C: 0x00000000 (1 start, 1 end) TRANS_HSYNC_C: 0x00000000 (1 start, 1 end) TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total) TRANS_VBLANK_C: 0x00000000 (1 start, 1 end) TRANS_VSYNC_C: 0x00000000 (1 start, 1 end) TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0) TRANSC_DATA_N1: 0x00000000 (val 0x0 0) TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0) TRANSC_DATA_N2: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0) TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0) TRANSACONF: 0xc0000000 (enable, active) TRANSBCONF: 0xc0000000 (enable, active) TRANSCCONF: 0x00000000 (disable, inactive) FDI_TXA_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable) FDI_TXB_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable) FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable) FDI_RXA_CTL: 0x80022350 (enable, train pattern pattern_1, port width X1, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk) FDI_RXB_CTL: 0x80002350 (enable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk) FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk) FDI_RXA_MISC: 0x00000080 (FDI Delay 128) FDI_RXB_MISC: 0x00000080 (FDI Delay 128) FDI_RXC_MISC: 0x00000080 (FDI Delay 128) FDI_RXA_TUSIZE1: 0x7e000000 FDI_RXA_TUSIZE2: 0x7e000000 FDI_RXB_TUSIZE1: 0x7e000000 FDI_RXB_TUSIZE2: 0x7e000000 FDI_RXC_TUSIZE1: 0x7e000000 FDI_RXC_TUSIZE2: 0x7e000000 FDI_PLL_CTL_1: 0x7e000000 FDI_PLL_CTL_2: 0x7e000000 FDI_RXA_IIR: 0x00000000 FDI_RXA_IMR: 0x000008ff FDI_RXB_IIR: 0x00000000 FDI_RXB_IMR: 0x000008ff PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync) HDMIB: 0xa0000adc (enabled pipe A 8bpc TMDS HDMI audio enabled +vsync +hsync detected) HDMIC: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected) HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected) PCH_LVDS: 0x80200302 (enabled, pipe A, 18 bit, 1 channel) CPU_eDP_A: 0x00000018 PCH_DP_B: 0x00000004 PCH_DP_C: 0x00000004 PCH_DP_D: 0x00000004 TRANS_DP_CTL_A: 0x60000418 (enabled, pipe A, 18 bit, 1 channel) TRANS_DP_CTL_B: 0x60000018 (enabled, pipe A, 18 bit, 1 channel) TRANS_DP_CTL_C: 0x60000018 (enabled, pipe A, 18 bit, 1 channel) BLC_PWM_CPU_CTL2: 0x80000000 BLC_PWM_CPU_CTL: 0x00001228 BLC_PWM_PCH_CTL1: 0x80000000 BLC_PWM_PCH_CTL2: 0x12281228 PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle) PCH_PP_CONTROL: 0xabcd0003 (blacklight disabled, power down on reset, panel on) PCH_PP_ON_DELAYS: 0x012c0bb8 PCH_PP_OFF_DELAYS: 0x012c07d0 PCH_PP_DIVISOR: 0x00186906
