On Fri, Jan 27, 2012 at 12:56:23AM -0200, Paulo Zanoni wrote: > Hi > > 2012/1/26 Daniel Vetter <daniel.vetter at ffwll.ch>: > > Hi all, > > > > http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced > > > > I just tested your patch set and it didn't work: my monitor reported > 1920x539 at 50Hz. We're missing something from patch "fixup interlace > vertical timings confusion". The reg dump is attached. > > By the way, VTOTAL_B was 1078. We need to remove those "-1" and also > those "-2". Look at ironlake_crtc_mode_set: we already do the > subtractions when we write to HSYNC, HTOTAL, etc. From the register > descriptions, those -1 are independent of interlaced or > non-interlaced. I believe there was some confusion with these > registers because intel_reg_dumper already re-adds +1 when showing the > register values. Ok, so something is still botched up :( Btw I think VSYNCSHIFT is only used by analog outputs to place the 2nd field lines exactly between the lines of the 1st field. Can you also please attach a reg dump with Peter's patch so I can compare? Thanks, Daniel -- Daniel Vetter Mail: daniel at ffwll.ch Mobile: +41 (0)79 365 57 48
