s/Arun/Jeff + Jon/
This W/A would seem to be breaking context isolation as it is not context saved. Thus it is a candidate for being removed.
I have to say I did not get any wiser from reading the HSD, so can you guys bring some insight here?
Regards, Joonas
On Wed, 2017-11-01 at 22:44 +0000, Chris Wilson wrote:
> Quoting Arun Siluvery (2016-06-03 12:40:00)
> > Kernel only need to add a register to HW whitelist, required for a
> > preemption related issue.
> >
> > Reference: HSD#2131039
> > Signed-off-by: Arun Siluvery <arun.siluvery@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++
> > 2 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e307725..1f6040a 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -6072,6 +6072,7 @@ enum skl_disp_power_wells {
> > #define GEN9_TSG_BARRIER_ACK_DISABLE (1<<8)
> >
> > #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec)
> > +#define GEN9_CTX_PREEMPT_REG _MMIO(0x2248)
> > #define GEN8_CS_CHICKEN1 _MMIO(0x2580)
> >
> > /* GEN7 chicken */
> > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > index 8d35a39..1f9d3a4 100644
> > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> > @@ -987,6 +987,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> > I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
> > GEN8_LQSC_FLUSH_COHERENT_LINES));
> >
> > + /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
> > + ret= wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
> > + if (ret)
> > + return ret;
>
> What is for exactly? This register is not context saved, so...
> -Chris
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--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
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