Quoting Michal Wajdeczko (2017-10-24 11:50:56)
> Waiting for DMA status register can be done with dedicated function.
> Lets use it as additional bonus will be smaller driver footprint.
>
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx>
> Cc: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_huc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
> index c8a48cb..98d1725 100644
> --- a/drivers/gpu/drm/i915/intel_huc.c
> +++ b/drivers/gpu/drm/i915/intel_huc.c
> @@ -151,7 +151,7 @@ static int huc_ucode_xfer(struct intel_uc_fw *huc_fw, struct i915_vma *vma)
> I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
>
> /* Wait for DMA to finish */
> - ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
> + ret = intel_wait_for_register_fw(dev_priv, DMA_CTRL, START_DMA, 0, 100);
>
> DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
Reviewed-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Aside, what's the serialisation so that we only try to load one fw at a
time?
-Chris
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