Quoting Chris Wilson (2017-10-24 12:07:58)
> A new context assumes that all of its registers are in the default state
> when it is created. What may happen is that a register written by one
> context may leak into the second, causing mass confusion.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> ---
> tests/Makefile.sources | 1 +
> tests/gem_ctx_isolation.c | 351 ++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 352 insertions(+)
> create mode 100644 tests/gem_ctx_isolation.c
>
> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
> index ac9f90bc..d18b7461 100644
> --- a/tests/Makefile.sources
> +++ b/tests/Makefile.sources
> @@ -57,6 +57,7 @@ TESTS_progs = \
> gem_ctx_basic \
> gem_ctx_create \
> gem_ctx_exec \
> + gem_ctx_isolation \
> gem_ctx_param \
> gem_ctx_switch \
> gem_ctx_thrash \
> diff --git a/tests/gem_ctx_isolation.c b/tests/gem_ctx_isolation.c
> new file mode 100644
> index 00000000..1569f5a8
> --- /dev/null
> +++ b/tests/gem_ctx_isolation.c
> @@ -0,0 +1,351 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "igt.h"
> +#include "igt_dummyload.h"
> +
> +#define MAX_REG 0x40000
> +#define NUM_REGS (MAX_REG / sizeof(uint32_t))
> +
> +#define PAGE_ALIGN(x) ALIGN(x, 4096)
> +
> +#define DIRTY 0x1
> +#define UNSAFE 0x2
> +
> +enum {
> + RCS_MASK = 0x1,
> + BCS_MASK = 0x2,
> + VCS_MASK = 0x4,
> + VECS_MASK = 0x8,
> +};
We be nice to include these in the future intel_engine interface!
> +#define ALL ~0u
> +#define GEN_RANGE(x, y) ((ALL >> (32 - (y - x + 1))) << x)
> +
> +static const struct named_register {
> + const char *name;
> + unsigned int gen_mask;
> + unsigned int engine_mask;
> + uint32_t offset;
> +} safe_registers[] = {
This list is incomplete, we need the list of nonpriv registers.
> + /* Keep in ascending offset order */
> + { "CTX_PREEMPT", GEN_RANGE(9, 10), RCS_MASK, 0x2248 },
> + { "CS_CHICKEN1", GEN_RANGE(9, 10), RCS_MASK, 0x2580 },
> + { "HDC_CHICKEN1", GEN_RANGE(9, 10), RCS_MASK, 0x7304 },
> + { "L3SQREG1", GEN_RANGE(8, 10), RCS_MASK, 0xb010 },
> + {}
> +}, ignore_registers[] = {
> + { "RCS timestamp", ALL, RCS_MASK, 0x2358 },
> + { "VCS0 timestamp", ALL, VCS_MASK, 0x12358 },
> + { "VCS1 timestamp", ALL, VCS_MASK, 0x1c358 },
> + { "BCS timestamp", ALL, BCS_MASK, 0x22358 },
> + { "VECS timestamp", ALL, VECS_MASK, 0x1a358 },
> + {}
> +};
> +igt_main
> +{
> + const unsigned int platform_validation = 0;
So UNSAFE is decidedly unsafe; is there anyway we can run tests only
during PV?
> + int fd = -1;
> +
> + igt_fixture {
> + fd = drm_open_driver(DRIVER_INTEL);
> + igt_require_gem(fd);
> +
> + igt_require(gem_has_execlists(fd));
And we need an igt_ci_fail_on(gen >= KNOWN_GEN);
> + /* check that we can create contexts. */
> + gem_context_destroy(fd, gem_context_create(fd));
> + }
-Chris
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