On Wed, Oct 18, 2017 at 08:48:23PM +0000, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Track the system agent voltage we request from pcode in the cdclk state
> on BXT/GLK. Annoyingly we can't actually read out the current value since
> there's no pcode command to do that, so we'll have to just assume that
> it worked.
>
> Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_cdclk.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 6f7b5abe6e3f..1b4dcd9689da 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1166,6 +1166,11 @@ static int glk_calc_cdclk(int min_cdclk)
> return 79200;
> }
>
> +static u8 bxt_calc_voltage(int cdclk)
> +{
> + return DIV_ROUND_UP(cdclk, 25000);
> +}
> +
> static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
> {
> int ratio;
> @@ -1242,7 +1247,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> cdclk_state->cdclk = cdclk_state->ref;
>
> if (cdclk_state->vco == 0)
> - return;
> + goto out;
>
> divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
>
> @@ -1266,6 +1271,13 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
> }
>
> cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
> +
> + out:
> + /*
> + * Can't read this out :( Let's assume it's
> + * at least what the CDCLK frequency requires.
> + */
> + cdclk_state->voltage = bxt_calc_voltage(cdclk_state->cdclk);
> }
>
> static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> @@ -1368,7 +1380,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>
> mutex_lock(&dev_priv->pcu_lock);
> ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
> - DIV_ROUND_UP(cdclk, 25000));
> + cdclk_state->voltage);
> mutex_unlock(&dev_priv->pcu_lock);
>
> if (ret) {
> @@ -1460,6 +1472,7 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
> cdclk_state.cdclk = bxt_calc_cdclk(0);
> cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
> }
> + cdclk_state.voltage = bxt_calc_voltage(cdclk_state.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_state);
> }
> @@ -1477,6 +1490,7 @@ void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
>
> cdclk_state.cdclk = cdclk_state.ref;
> cdclk_state.vco = 0;
> + cdclk_state.voltage = bxt_calc_voltage(cdclk_state.cdclk);
>
> bxt_set_cdclk(dev_priv, &cdclk_state);
> }
> @@ -2030,6 +2044,7 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> intel_state->cdclk.logical.vco = vco;
> intel_state->cdclk.logical.cdclk = cdclk;
> + intel_state->cdclk.logical.voltage = bxt_calc_voltage(cdclk);
>
> if (!intel_state->active_crtcs) {
> if (IS_GEMINILAKE(dev_priv)) {
> @@ -2042,6 +2057,7 @@ static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
>
> intel_state->cdclk.actual.vco = vco;
> intel_state->cdclk.actual.cdclk = cdclk;
> + intel_state->cdclk.actual.voltage = bxt_calc_voltage(cdclk);
> } else {
> intel_state->cdclk.actual =
> intel_state->cdclk.logical;
> --
> 2.13.6
>
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