From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> Here's my idea on how the CNL DVFS thing ought to be implemented. Not sure I gleaned the details of the port clock limits correctly, but other than that I think this should work. Entire series available here: git://github.com/vsyrjala/linux.git dvfs_voltage_4 Cc: Mika Kahola <mika.kahola@xxxxxxxxx> Cc: Manasi Navare <manasi.d.navare@xxxxxxxxx> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> Ville Syrjälä (8): drm/i915: Clean up some cdclk switch statements drm/i915: Start tracking voltage level in the cdclk state drm/i915: USe cdclk_state->voltage on VLV/CHV drm/i915: Use cdclk_state->voltage on BDW drm/i915: Use cdclk_state->voltage on SKL/KBL/CFL drm/i915: Use cdclk_state->voltage on BXT/GLK drm/i915: Use cdclk_state->voltage on CNL drm/i915: Adjust system agent voltage on CNL if required by DDI ports drivers/gpu/drm/i915/i915_drv.h | 3 + drivers/gpu/drm/i915/intel_cdclk.c | 318 +++++++++++++++++++++++--------- drivers/gpu/drm/i915/intel_ddi.c | 13 ++ drivers/gpu/drm/i915/intel_display.c | 14 +- drivers/gpu/drm/i915/intel_dp_mst.c | 5 + drivers/gpu/drm/i915/intel_drv.h | 10 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +- 7 files changed, 276 insertions(+), 90 deletions(-) -- 2.13.6 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
