Spec tells us to change the level "if the frequency will result
in a change to the voltage requirement."
When we don't have pll enabled yet we only base our level
calculation on cdclk. So let's do the same when disabling the
pll instead of forcing randomly to zero.
Cc: Mika Kahola <mika.kahola@xxxxxxxxx>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 25 +++++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index ca1ea475c517..f6b58879ac6a 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2060,7 +2060,9 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
uint32_t val;
- int ret;
+ int ret = 0;
+ int cdclk, level;
+ bool change_level;
/*
* 1. Configure DPCLKA_CFGCR0 to turn off the clock for the DDI.
@@ -2072,7 +2074,22 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* (DVFS) Sequence Before Frequency Change
*/
- ret = cnl_dvfs_pre_change(dev_priv);
+ cdclk = dev_priv->cdclk.hw.cdclk;
+ switch (cdclk) {
+ case 528000:
+ level = 2;
+ break;
+ case 336000:
+ level = 1;
+ break;
+ case 168000:
+ default:
+ level = 0;
+ break;
+ }
+ change_level = cnl_dvfs_need_change(dev_priv, level);
+ if (change_level)
+ ret = cnl_dvfs_pre_change(dev_priv);
/* 3. Disable DPLL through DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2092,8 +2109,8 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* (DVFS) Sequence After Frequency Change
*/
- if (ret == 0)
- cnl_dvfs_post_change(dev_priv, 0);
+ if (change_level && ret == 0)
+ cnl_dvfs_post_change(dev_priv, level);
/* 6. Disable DPLL power in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
--
2.13.5
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