This is a new attempt of fixing the DVFS on CNL.
After I got the CI nack on the initial attempt I went down
finding and fixing some issues.
But also I decided to rework the existent port clock
functions to make sure we don't duplicate existent code
but also make sure we address HDMI case.
Another difference is that this series I don't extend
dvfs functions to SKL yet. I'd like to first discuss
and fix this CNL before we go and address SKL one.
Along with extending to SKL my plan is to document
these dvfs functions.
So, please let me know all your thoughts about patches here.
Thanks in advance,
Rodrigo.
Kahola, Mika (3):
drm/i915/cnl: Expose DVFS change functions
drm/i915/cnl: DVFS for PLL enabling
drm/i915/cnl: DVFS for PLL disabling
Paulo Zanoni (1):
drm/i915/cnl: extract cnl_dvfs_{pre,post}_change
Rodrigo Vivi (8):
drm/i915: Let's use more enum intel_dpll_id pll_id.
drm/i915/cnl: Extract cnl_calc_pll_link following bxt style.
drm/i915/skl: Extract cnl_calc_pll_link following bxt,cnl style.
drm/i915: Unify and export gen9+ port_clock calculation.
drm/i915/cnl: Only request voltage frequency switching when needed.
drm/i915/cnl: When disabling pll put dvfs back to cdclk requirement.
drm/i915/cnl: Invert dvfs default level.
drm/i915/cnl: Unify dvfs level selection.
drivers/gpu/drm/i915/intel_cdclk.c | 66 +++++++++++++++++---------
drivers/gpu/drm/i915/intel_ddi.c | 87 +++++++++++++++++++++++------------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 42 ++++++++++-------
drivers/gpu/drm/i915/intel_drv.h | 7 ++-
4 files changed, 133 insertions(+), 69 deletions(-)
--
2.13.5
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