From: "Kahola, Mika" <mika.kahola@xxxxxxxxx>
Display Voltage and Frequency Switching (DVFS) is used to adjust the
display voltage to match the display clock frequencies. If voltage is
set too low, it will break functionality. If voltage is set too high,
it will waste power. Voltage level is selected based on CD clock and
DDI clock.
The sequence before frequency change is the following and it requests
the power controller to raise voltage to maximum
- Ensure any previous GT Driver Mailbox transaction is complete.
- Write GT Driver Mailbox Data Low = 0x3.
- Write GT Driver Mailbox Data High = 0x0.
- Write GT Driver Mailbox Interface = 0x80000007.
- Poll GT Driver Mailbox Interface for Run/Busy indication cleared (bit 31 = 0).
- Read GT Driver Mailbox Data Low, if bit 0 is 0x1, continue, else restart the sequence.
Timeout after 3ms
The sequence after frequency change is the following and it requests
the port controller to raise voltage to the requested level.
- Write GT Driver Mailbox Data Low
* For level 0, write 0x0
* For level 1, write 0x1
* For level 2, write 0x2
* For level 3, write 0x3
- Write GT Driver Mailbox Data High = 0x0.
- Write GT Driver Mailbox Interface = 0x80000007.
For Cannonlake, the level 3 is not used and it aliases to level 2.
v2: reuse Paulo's work on cdclk. This patch depends on Paulo's patch
[PATCH 02/12] drm/i915/cnl: extract cnl_dvfs_{pre,post}_change
v3: (By Rodrigo): Remove duplicated commend and fix typo on Paulo's name.
Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Signed-off-by: Kahola, Mika <mika.kahola@xxxxxxxxx>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 57 ++++++++++++++++++++++++++++++-----
1 file changed, 49 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index a2a3d93d67bd..9927df6294da 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1966,10 +1966,48 @@ static const struct intel_dpll_mgr bxt_pll_mgr = {
.dump_hw_state = bxt_dump_hw_state,
};
+static int cnl_get_port_clock(uint32_t val)
+{
+ if (val & DPLL_CFGCR0_LINK_RATE_810)
+ return 2*81000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_1350)
+ return 2*135000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_2700)
+ return 2*270000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_1620)
+ return 2*162000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_1080)
+ return 2*108000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_2160)
+ return 2*216000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_3240)
+ return 2*324000;
+ else if (val & DPLL_CFGCR0_LINK_RATE_4050)
+ return 2*405000;
+
+ return -EINVAL;
+}
+
+static int cnl_get_dvfs_level(int cdclk, int portclk)
+{
+ if (portclk == -EINVAL)
+ return 2;
+
+ if (cdclk == 168000 && portclk < 594000)
+ return 0;
+ else if (cdclk == 336000 && portclk < 594000)
+ return 1;
+ else
+ return 2;
+}
+
static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
struct intel_shared_dpll *pll)
{
uint32_t val;
+ int ret;
+ int level;
+ int cdclk, portclk;
/* 1. Enable DPLL power in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2006,11 +2044,9 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
/*
* 5. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
- * Sequence Before Frequency Change
- *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * (DVFS) Sequence Before Frequency Change
*/
+ ret = cnl_dvfs_pre_change(dev_priv);
/* 6. Enable DPLL in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2028,11 +2064,16 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
/*
* 8. If the frequency will result in a change to the voltage
* requirement, follow the Display Voltage Frequency Switching
- * Sequence After Frequency Change
- *
- * FIXME: (DVFS) is used to adjust the display voltage to match the
- * display clock frequencies
+ * (DVFS) Sequence After Frequency Change
*/
+ if (ret == 0) {
+ val = pll->state.hw_state.cfgcr0;
+ cdclk = dev_priv->cdclk.hw.cdclk;
+ portclk = cnl_get_port_clock(val);
+
+ level = cnl_get_dvfs_level(cdclk, portclk);
+ cnl_dvfs_post_change(dev_priv, level);
+ }
/*
* 9. turn on the clock for the DDI and map the DPLL to the DDI
--
2.13.5
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