Although SKL Spec doesn't explicit call this sequence
as DVFS, that is exactly what it is.
So let's remove a bit of code duplication and re-use
CNL functions.
No functional change.
Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_cdclk.c | 25 ++++++-------------------
drivers/gpu/drm/i915/intel_dpll_mgr.c | 8 ++++----
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
3 files changed, 12 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 86ef4d0add70..d6befabd6ed5 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -924,21 +924,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
int cdclk = cdclk_state->cdclk;
int vco = cdclk_state->vco;
u32 freq_select, pcu_ack;
- int ret;
WARN_ON((cdclk == 24000) != (vco == 0));
- mutex_lock(&dev_priv->rps.hw_lock);
- ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
- SKL_CDCLK_PREPARE_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE,
- SKL_CDCLK_READY_FOR_CHANGE, 3);
- mutex_unlock(&dev_priv->rps.hw_lock);
- if (ret) {
- DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
- ret);
- return;
- }
+ skl_dvfs_pre_change(dev_priv);
/* set CDCLK_CTL */
switch (cdclk) {
@@ -975,9 +964,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
POSTING_READ(CDCLK_CTL);
/* inform PCU of the change */
- mutex_lock(&dev_priv->rps.hw_lock);
- sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
- mutex_unlock(&dev_priv->rps.hw_lock);
+ skl_dvfs_post_change(dev_priv, pcu_ack);
intel_update_cdclk(dev_priv);
}
@@ -1510,7 +1497,7 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
dev_priv->cdclk.hw.vco = vco;
}
-int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
+int skl_dvfs_pre_change(struct drm_i915_private *dev_priv)
{
int ret;
@@ -1528,7 +1515,7 @@ int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv)
return ret;
}
-void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
+void skl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
{
mutex_lock(&dev_priv->rps.hw_lock);
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, level);
@@ -1542,7 +1529,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
int vco = cdclk_state->vco;
u32 val, divider, pcu_ack;
- if (!cnl_dvfs_pre_change(dev_priv))
+ if (!skl_dvfs_pre_change(dev_priv))
return;
/* cdclk = vco / 2 / div{1,2} */
@@ -1590,7 +1577,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
I915_WRITE(CDCLK_CTL, val);
/* inform PCU of the change */
- cnl_dvfs_post_change(dev_priv, pcu_ack);
+ skl_dvfs_post_change(dev_priv, pcu_ack);
intel_update_cdclk(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index cc288534dcc6..c08ca8f03e90 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2046,7 +2046,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* (DVFS) Sequence Before Frequency Change
*/
- ret = cnl_dvfs_pre_change(dev_priv);
+ ret = skl_dvfs_pre_change(dev_priv);
/* 6. Enable DPLL in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2072,7 +2072,7 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
portclk = cnl_get_port_clock(val);
level = cnl_get_dvfs_level(cdclk, portclk);
- cnl_dvfs_post_change(dev_priv, level);
+ skl_dvfs_post_change(dev_priv, level);
}
/*
@@ -2097,7 +2097,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
* requirement, follow the Display Voltage Frequency Switching
* (DVFS) Sequence Before Frequency Change
*/
- ret = cnl_dvfs_pre_change(dev_priv);
+ ret = skl_dvfs_pre_change(dev_priv);
/* 3. Disable DPLL through DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2118,7 +2118,7 @@ static void cnl_ddi_pll_disable(struct drm_i915_private *dev_priv,
* (DVFS) Sequence After Frequency Change
*/
if (ret == 0)
- cnl_dvfs_post_change(dev_priv, 0);
+ skl_dvfs_post_change(dev_priv, 0);
/* 6. Disable DPLL power in DPLL_ENABLE. */
val = I915_READ(CNL_DPLL_ENABLE(pll->id));
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f9d7b48584d3..688843bd7f68 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1320,10 +1320,10 @@ void intel_audio_deinit(struct drm_i915_private *dev_priv);
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
void skl_init_cdclk(struct drm_i915_private *dev_priv);
void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
+int skl_dvfs_pre_change(struct drm_i915_private *dev_priv);
+void skl_dvfs_post_change(struct drm_i915_private *dev_priv, int level);
void cnl_init_cdclk(struct drm_i915_private *dev_priv);
void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
-int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv);
-void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level);
void bxt_init_cdclk(struct drm_i915_private *dev_priv);
void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
--
2.13.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
