I see. Thanks for the explanation! :) -----Original Message----- From: Joonas Lahtinen [mailto:joonas.lahtinen@xxxxxxxxxxxxxxx] Sent: Thursday, August 31, 2017 5:20 PM To: Wang, Zhi A <zhi.a.wang@xxxxxxxxx>; Vivi, Rodrigo <rodrigo.vivi@xxxxxxxxx> Cc: intel-gfx@xxxxxxxxxxxxxxxxxxxxx; zhenyuw@xxxxxxxxxxxxxxx; intel-gvt-dev@xxxxxxxxxxxxxxxxxxxxx; chris@xxxxxxxxxxxxxxxxxx; Widawsky, Benjamin <benjamin.widawsky@xxxxxxxxx> Subject: Re: [RFCv6 2/2] drm/i915: Introduce private PAT management On Thu, 2017-08-31 at 08:28 +0000, Wang, Zhi A wrote: > Do you mean I still keep I915_WRITE(xxxxx) in xxxx_setup_private_pat() like before? Then changed them in a new patch? No, I mean use the new code structure, but make sure all register writes are equal to what they were before (and please send a separate patch for the CNL caching issue before that). Regards, Joonas -- Joonas Lahtinen Open Source Technology Center Intel Corporation _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
