Quoting Daniel Vetter (2017-08-18 09:12:12)
> On Thu, Aug 17, 2017 at 06:32:29PM +0100, Chris Wilson wrote:
> > Forcewake is not affected by the engine reset on gen6+. Indeed the
> > reason why we added intel_uncore_forcewake_reset() to
> > gen6_reset_engines() was to keep the bookkeeping intact because the
> > reset did not touch the forcewake bit (yet we cancelled the forcewake
> > consumers)! This was done in commit 521198a2e7095:
> > Author: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> > Date: Fri Aug 23 16:52:30 2013 +0300
> >
> > drm/i915: sanitize forcewake registers on reset
> >
> > In reset we try to restore the forcewake state to
> > pre reset state, using forcewake_count. The reset
> > doesn't seem to clear the forcewake bits so we
> > get warn on forcewake ack register not clearing.
> >
> > That futzing of the forcewake bookkeeping was dropped in commit
> > 0294ae7b44bb ("drm/i915: Consolidate forcewake resetting to a single
> > function"), but it did not make the realisation that the remaining
> > intel_uncore_forcewake_reset() was redundant.
> >
> > The new danger with using intel_uncore_forcewake_reset() with per-engine
> > resets is that the driver and hw are still in an active state as we
> > perform the reset. We may be using the forcewake to read protected
> > registers elsewhere and those results may be clobbered by the concurrent
> > dropping of forcewake.
> >
> > Reported-by: Michel Thierry <michel.thierry@xxxxxxxxx>
> > Fixes: 142bc7d99bcf ("drm/i915: Modify error handler for per engine hang recovery")
> > Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> > Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
> > Cc: Michel Thierry <michel.thierry@xxxxxxxxx>
>
> Could this explain some of the random unclaimed register failures we're
> seeing on hsw shard CI?
>
> https://bugs.freedesktop.org/show_bug.cgi?id=102249
>
> Otoh this is in the display well, but maybe we're just racing and it's
> just a stale bit in the unclaimed mmio debugging stuff. Worth a
> References: I think.
No. Those registers are outside of the forcewake domain. I was hoping
this might explain the kbl reset failures, but the only trace there I
saw was the GPU reset request timing out i.e. gen6_hw_domain_reset()
which is before the fw reset.
-Chris
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