From: Clint Taylor <clinton.a.taylor@xxxxxxxxx> DDIA Lane capability control 4 lane bit is not being set by firmware during clone mode boot. This occurs when multiple monitors are connected during boot. The driver will configure the port for 2 lane maximum width if this bit is not set. Once DDIA/E lane split is supported in vbt and the i915 driver we will need to revisit this code. Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> Signed-off-by: Clint Taylor <clinton.a.taylor@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_ddi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 494fbe0..e7644b4 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2713,9 +2713,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) * configuration so that we use the proper lane count for our * calculations. */ - if (IS_GEN9_LP(dev_priv) && port == PORT_A) { + if ((IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) && + port == PORT_A) { if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) { - DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n"); + DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n"); intel_dig_port->saved_port_bits |= DDI_A_4_LANES; max_lanes = 4; } -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx