On Thu, Jul 06, 2017 at 05:40:35PM +0300, Imre Deak wrote:
> The pattern of a power well backing a set of pipe IRQ or VGA
> functionality applies to all HSW+ platforms. Using power well attributes
> instead of platform checks to decide whether to init/reset pipe IRQs and
> VGA correspondingly is cleaner and it allows us to unify the HSW/BDW and
> GEN9+ power well code in follow-up patches.
>
> Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
> drivers/gpu/drm/i915/intel_runtime_pm.c | 34 ++++++++++++++++++++-------------
> 2 files changed, 27 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b27f2fc..dc5ca5a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1391,6 +1391,12 @@ struct i915_power_well {
> struct {
> enum dpio_phy phy;
> } bxt;
> + struct {
> + /* Mask of pipes whose IRQ logic is backed by the pw */
> + u32 irq_pipe_mask;
u8 would be plenty. Might help keep the size down by a few bytes.
> + /* The pw is backing the VGA functionality */
> + bool has_vga:1;
> + } hsw;
> };
> const struct i915_power_well_ops *ops;
> };
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index e18c38e6..ab2e0ee 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -281,7 +281,8 @@ void intel_display_set_init_power(struct drm_i915_private *dev_priv,
> * to be enabled, and it will only be disabled if none of the registers is
> * requesting it to be enabled.
> */
> -static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
> +static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
> + u32 irq_pipe_mask, bool has_vga)
> {
> struct pci_dev *pdev = dev_priv->drm.pdev;
>
> @@ -295,20 +296,21 @@ static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
> * sure vgacon can keep working normally without triggering interrupts
> * and error messages.
> */
> - vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> - outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
> - vga_put(pdev, VGA_RSRC_LEGACY_IO);
> + if (has_vga) {
> + vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
> + outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
> + vga_put(pdev, VGA_RSRC_LEGACY_IO);
> + }
>
> - if (IS_BROADWELL(dev_priv))
> - gen8_irq_power_well_post_enable(dev_priv,
> - 1 << PIPE_C | 1 << PIPE_B);
> + if (irq_pipe_mask)
> + gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
> }
>
> -static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
> +static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
> + u32 irq_pipe_mask)
> {
> - if (IS_BROADWELL(dev_priv))
> - gen8_irq_power_well_pre_disable(dev_priv,
> - 1 << PIPE_C | 1 << PIPE_B);
> + if (irq_pipe_mask)
> + gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
> }
>
> static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
> @@ -413,7 +415,9 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> HSW_PWR_WELL_CTL_STATE(id),
> 20))
> DRM_ERROR("Timeout enabling power well\n");
> - hsw_power_well_post_enable(dev_priv);
> +
> + hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask,
> + power_well->hsw.has_vga);
> }
>
> static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
> @@ -422,7 +426,8 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
> enum i915_power_well_id id = power_well->id;
> u32 val;
>
> - hsw_power_well_pre_disable(dev_priv);
> + hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask);
> +
> val = I915_READ(HSW_PWR_WELL_DRIVER);
> I915_WRITE(HSW_PWR_WELL_DRIVER, val & ~HSW_PWR_WELL_CTL_REQ(id));
> POSTING_READ(HSW_PWR_WELL_DRIVER);
> @@ -2057,6 +2062,7 @@ static struct i915_power_well hsw_power_wells[] = {
> .domains = HSW_DISPLAY_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = HSW_DISP_PW_GLOBAL,
> + .hsw.has_vga = true,
> },
> };
>
> @@ -2073,6 +2079,8 @@ static struct i915_power_well bdw_power_wells[] = {
> .domains = BDW_DISPLAY_POWER_DOMAINS,
> .ops = &hsw_power_well_ops,
> .id = HSW_DISP_PW_GLOBAL,
> + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> + .hsw.has_vga = true,
> },
> };
>
> --
> 2.7.4
>
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> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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