The programming of display power wells starting from HSW is pretty
similar on all platforms, but we have separate code for HSW/BDW and
GEN9+ platforms. This patchset unifies the two for clarity and to make
it easier to add power well support for future platforms. In essence
this means adding 3 attributes, irq_pipe_mask, has_vga and has_fuses
to the power well struct and perform the power well enable/disable
sequence steps selectively depending on these.
Imre Deak (18):
drm/i915/chv: Add unique power well ID for the pipe A power well
drm/i915: Unify power well ID enums
drm/i915: Assign everywhere the always-on power well ID
drm/i915/gen2: Add an ID for the display pipes power well
drm/i915/hsw,bdw: Add an ID for the global display power well
drm/i915: Check for duplicated power well IDs
drm/i915/bxt,glk: Give a proper name to the power well struct phy
field
drm/i915/gen9+: Remove redundant power well state assert during
enabling
drm/i915/gen9+: Remove redundant state check during power well
toggling
drm/i915/hsw,bdw: Remove redundant state check during power well
toggling
drm/i915/hsw,bdw: Split power well set to enable/disable helpers
drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
drm/i915/hsw,bdw: Add irq_pipe_mask, has_vga power well attributes
drm/i915/hsw,bdw: Wait for the power well disabled state
drm/i915/hsw+: Add has_fuses power well attribute
drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers
drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers
drm/i915: Gather all the power well->domain mappings to one place
drivers/gpu/drm/i915/gvt/display.c | 6 +-
drivers/gpu/drm/i915/gvt/handlers.c | 8 +-
drivers/gpu/drm/i915/i915_drv.h | 15 +-
drivers/gpu/drm/i915/i915_reg.h | 69 ++-
drivers/gpu/drm/i915/intel_runtime_pm.c | 886 ++++++++++++++------------------
5 files changed, 450 insertions(+), 534 deletions(-)
--
2.7.4
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