iirc I assumed 1 pixel per clk for CNL when I originally submitted the workaround patch because cnl_xxx_calc_cdclk() functions assume that. Are we missing something in the cdclk setup code to enable 2 pixels per clk?
-DK
________________________________________
From: Ville Syrjälä [ville.syrjala@xxxxxxxxxxxxxxx]
Sent: Friday, July 07, 2017 11:24 AM
To: Rodrigo Vivi
Cc: intel-gfx; Pandiyan, Dhinakaran; Zanoni, Paulo R; Vivi, Rodrigo
Subject: Re: [PATCH 1/3] drm/i915: Fix up CNL cdclk related limits
On Fri, Jul 07, 2017 at 10:54:47AM -0700, Rodrigo Vivi wrote:
> I will review the series more carefully later,
> but my concern is that with this series applied I got a blank screen on eDP...
Hmm. Oh, I guess we could now be going for a lower cdclk that before
since we now account for 2 pixels per clock factor, whereas previously
didn't. That in itself should be fine of course, but I guess the
difference could be down to the system agent DVFS, which we still don't
handle it seems. So possibly we need to get that sorted before we can
change how CNL picks its cdclk.
>
>
> On Fri, Jul 7, 2017 at 3:24 AM, <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> > From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> >
> > Follow the GLK path when computing cdclk and related limits. CNL
> > pipes also produce two pixels per clock, so that's what we should
> > use.
> >
> > For the HBR2 vs. audio issue the limit should more correctly be 336
> > MHz, but the GLK limit of 316.8 MHz works just as well and results
> > in picking at least 336 MHz. Also toss in some related w/a numbers.
> >
> > Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> > Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/i915/intel_cdclk.c | 15 +++++++++------
> > 1 file changed, 9 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> > index 1241e5891b29..9e0deebae279 100644
> > --- a/drivers/gpu/drm/i915/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> > @@ -1752,12 +1752,13 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > crtc_state->has_audio &&
> > crtc_state->port_clock >= 540000 &&
> > crtc_state->lane_count == 4) {
> > - if (IS_CANNONLAKE(dev_priv))
> > - pixel_rate = max(316800, pixel_rate);
> > - else if (IS_GEMINILAKE(dev_priv))
> > + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> > + /* Display WA #1145: glk,cnl */
> > pixel_rate = max(2 * 316800, pixel_rate);
> > - else
> > + } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) {
> > + /* Display WA #1144: skl,bxt */
> > pixel_rate = max(432000, pixel_rate);
> > + }
> > }
> >
> > /* According to BSpec, "The CD clock frequency must be at least twice
> > @@ -1766,7 +1767,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> > * two pixels per clock.
> > */
> > if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
> > - if (IS_GEMINILAKE(dev_priv))
> > + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> > pixel_rate = max(2 * 2 * 96000, pixel_rate);
> > else
> > pixel_rate = max(2 * 96000, pixel_rate);
> > @@ -1999,7 +2000,9 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
> > {
> > int max_cdclk_freq = dev_priv->max_cdclk_freq;
> >
> > - if (IS_GEMINILAKE(dev_priv))
> > + if (IS_CANNONLAKE(dev_priv))
> > + return 2 * max_cdclk_freq;
> > + else if (IS_GEMINILAKE(dev_priv))
> > /*
> > * FIXME: Limiting to 99% as a temporary workaround. See
> > * glk_calc_cdclk() for details.
> > --
> > 2.13.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
--
Ville Syrjälä
Intel OTC
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