On Fri, Jul 07, 2017 at 01:24:49PM +0300, ville.syrjala@xxxxxxxxxxxxxxx wrote:
> From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
>
> Make the min_pixclk thing less confusing by changing it to track
> the minimum acceptable cdclk frequency instead. This means moving
> the application of the guardbands to a slightly higher level from
> the low level platform specific calc_cdclk() functions.
>
> The immediate benefit is elimination of the confusing 2x factors
> on GLK/CNL+ in the audio workarounds (which stems from the fact
> that the pipes produce two pixels per clock).
>
> Cc: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 12 ++-
> drivers/gpu/drm/i915/intel_cdclk.c | 179 +++++++++++++++++------------------
> drivers/gpu/drm/i915/intel_display.c | 21 ++--
> drivers/gpu/drm/i915/intel_drv.h | 4 +-
> 4 files changed, 107 insertions(+), 109 deletions(-)
>
<snip>
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 9e0deebae279..82e5bc967cca 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -1732,21 +1723,47 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv,
> dev_priv->display.set_cdclk(dev_priv, cdclk_state);
> }
>
> -static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> - int pixel_rate)
> +static int intel_min_cdclk(struct drm_i915_private *dev_priv,
> + int pixel_rate)
> +{
> + if (INTEL_GEN(dev_priv) >= 10)
> + return DIV_ROUND_UP(pixel_rate, 2);
Rodrigo, so this part here could be why your CNL no longer works.
If you have time to try it, then I think changing this to just
'return pixel_rate;' should get us back to the old behaviour.
> + else if (IS_GEMINILAKE(dev_priv))
> + /*
> + * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
> + * as a temporary workaround. Use a higher cdclk instead. (Note that
> + * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
> + * cdclk.)
> + */
> + return DIV_ROUND_UP(pixel_rate * 100, 2 * 99);
> + else if (IS_GEN9(dev_priv) ||
> + IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> + return pixel_rate;
> + else if (IS_CHERRYVIEW(dev_priv))
> + return DIV_ROUND_UP(pixel_rate * 100, 95);
> + else
> + return DIV_ROUND_UP(pixel_rate * 100, 90);
> +}
> +
--
Ville Syrjälä
Intel OTC
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