"Disable all display engine functions using the full mode set disable sequence on all pipes, transcoders, ports, planes, and power well 2 (PG2)." I hope at this point we really already did all the rest besides the PG2. Anyways I believe this patch itself makes total sense so: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> On Thu, Jun 29, 2017 at 8:37 AM, Imre Deak <imre.deak@xxxxxxxxx> wrote: > What we want to assert based on the conditions required by Bspec is that > power well 2 is disabled, so no need to check for other power wells. > In addition we can only check if the driver's request is removed, the > actual state depends on whether the other request bits are set or not > (BIOS, KVMR, DEBUG). So check only the driver's request bit. > > Signed-off-by: Imre Deak <imre.deak@xxxxxxxxx> > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 8418879..1fc75e6 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -549,7 +549,9 @@ static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) > "DC9 already programmed to be enabled.\n"); > WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, > "DC5 still not disabled to enable DC9.\n"); > - WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); > + WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER) & > + SKL_POWER_WELL_REQ(SKL_DISP_PW_2), > + "Power well 2 on.\n"); > WARN_ONCE(intel_irqs_enabled(dev_priv), > "Interrupts not disabled yet.\n"); > > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
